MT46H8M32LFB5-75:A TR Micron Technology Inc, MT46H8M32LFB5-75:A TR Datasheet - Page 46

IC DDR SDRAM 256MBIT 90VFBGA

MT46H8M32LFB5-75:A TR

Manufacturer Part Number
MT46H8M32LFB5-75:A TR
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46H8M32LFB5-75:A TR

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 31:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
WRITE
Bank a,
Notes:
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. D
2. An interrupted burst of 8 is shown.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. PRE = PRECHARGE command.
6. DQS is required at T4 and T4n to register DM.
7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
D
t
b
WR is referenced from the first positive CK edge after the last data-in pair.
IN
IN
NOP
D
T1
b
b = data-in for column b.
IN
D
b
IN
T1n
NOP
T2
T2n
46
t
NOP
WR
T3
2
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
(a or all)
PRE
Bank
T4
Transitioning data
5
T4n
NOP
T5
©2005 Micron Technology, Inc. All rights reserved.
Don’t Care
T6
NOP
Operations

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