MT46H8M32LFB5-75:A TR Micron Technology Inc, MT46H8M32LFB5-75:A TR Datasheet - Page 36

• Manufacturer Part Number: MT46H8M32LFB5-75:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-75:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WRITEs
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
WRITE bursts are initiated with a WRITE command, as shown in Figure 21 on page 37.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(
clock cycle). All the WRITE diagrams show the nominal case, and where the two extreme
cases (for example,
also been included. Figure 22 on page 38 shows the nominal case and the extremes of
t
been initiated, the DQ will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied either
after the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 23 on page 39 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 24 on page 39. Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 25 on page 40.
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE without truncating the WRITE burst,
Figure 26 on page 41.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 27 on page 42. Note that only the data-in pairs that are registered prior to the
t
masked with DM, as shown in Figure 28 on page 43.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 29 on page 44. At least one clock cycle is required during
precharge mode.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 30 on page 45 and Figure 31 on page 46. Note that only the data-in pairs
that are registered prior to the
subsequent data-in should be masked with DM, as shown in Figures 30 and 31. After the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until
DQSS for a burst of 4. Upon completion of a burst, assuming no other commands have
WTR period are written to the internal array, and any subsequent data-in should be
t
DQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
t
RP is met.
t
DQSS [MIN] and
36
t
WR period are written to the internal array, and any
t
DQSS [MAX]) might not be intuitive, they have
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
WTR should be met, as shown in
t
WR should be met, as shown in
©2005 Micron Technology, Inc. All rights reserved.
t
WR time when in auto-
Operations