MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 7

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ball Description
Table 4:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
A8, B7, B8, C7, C8,
D3, C2, C3, B2, B3,
D7, D8, E7 E3, D2,
A7, B1, C9, D1, E9
J8, J9, K7, K8, K2,
K3, J1, J2, J3, J7,
Ball Numbers
A3, B9, C1, E1
G9, G8, G7
A9, F9, K9
A1, F1, K1
F3, F7, H3
G2, G3
H8, H9
H1, H2
E2, E7
F2, F8
G1
H7
A2
D9
60-Ball VFBGA Ball Description
UDQS, LDQS
RAS#, CAS#,
DQ0–DQ15
UDM, LDM
BA0, BA1
Symbol
CK, CK#
A0–A11
V
V
TEST
WE#
CKE
V
CS#
V
NC
DD
SS
DD
SS
Q
Q
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
Clock: CK is the system clock input. CK and CK# are differential clock inputs.
All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Input and output data is
referenced to the crossing of CK and CK# (both directions of the crossing).
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock signals, input buffers, and output drivers. Taking CKE LOW allows
PRECHARGE power-down and SELF REFRESH operations (all banks idle), or
ACTIVE power-down (row active in any bank). CKE is synchronous for all
functions expect SELF REFRESH exit. All input buffers (except CKE) are
disabled during power-down and self refresh modes.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks. CS#
is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are
input-only, the DM loading is designed to match that of DQ and DQS balls.
For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standard mode register or extended mode
register) is loaded during a LOAD MODE REGISTER command.
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ or WRITE commands,
to select one location out of the memory array in the respective bank.
During a PRECHARGE command, A10 determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data input/output: Data bus for x16.
Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. It is used to capture data.
DQ power supply.
DQ ground: Isolated on the die for improved noise immunity.
Power supply.
Ground.
No connect. These pins should be left unconnected.
Test pin: Must be tied to V
7
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
or V
Description
SS
Q in normal operations.
©2004 Micron Technology, Inc. All rights reserved.
Ball Description