MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 56

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 32:
Figure 33:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
COMMAND
All DQ values, collectively
Data Output Timing –
DQS, or LDQS/UDQS
Data Input Timing
Notes:
Notes:
CK#
CK
READ
T0
1. DQ transitioning after DQS transition define
2. All DQ must transition by
3.
DQS
1.
2.
3. WRITE command issued at T0.
4. LDQS controls the lower byte and UDQS controls the upper byte.
5. LDM controls the lower byte and UDM controls the upper byte.
DM
DQ
CK#
1
2
CK
t
t
t
4
5
AC is the DQ output window relative to CK, and is the “long term” component of DQ skew.
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
CL = 3
NOP
T1
T0
t DQSS
3
t
AC and
t WPRES
t DS
t AC (MAX)
t WPRE
NOP
T2
t DQSCK
t RPRE
t
T1
(MAX)
DI
b
DQSCK
t DSH 1
T2n
t DH
t
DQSQ after DQS transitions, regardless of
T1n
56
T2
t DQSL
t DSS 2
NOP
T3
T2
T2n
t
t DQSH t WPST
t
DQSS (MAX).
128Mb: 8 Meg x 16 Mobile DDR SDRAM
t DSH 1
DQSS (MIN).
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
t DQSCK
T3
(MAX)
t DSS 2
TRANSITIONING DATA
DON’T CARE
NOP
T4
t
DQSQ window.
T3
T3n
T4n
T4
NOP
T5
T4n
T5n
©2004 Micron Technology, Inc. All rights reserved.
t HZ (MAX)
Timing Diagrams
T5
t
AC.
NOP
T6
T5n
t RPST