MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 20

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8:
READs
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
COMMAND
BA0, BA1
A0-A11
CK#
CK
Example: Meeting
Bank x
Row
ACT
T0
READ bursts are initiated with a READ command, as shown in Figure 9 on page 21.
The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent data-
out element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 10 on page 22 shows general timing for each
possible CAS latency setting. DQS is driven by the Mobile DDR SDRAM along with
output data. The initial LOW state on DQS is known as the read preamble; the LOW state
coincident with the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of
window hold), the valid data window are depicted in Figure 31 on page 55. A detailed
explanation of
CK) is depicted in Figure 32 on page 56.
Data from any READ burst may be concatenated with or truncated with data from a
subsequent READ command. In either case, a continuous flow of data can be main-
tained. The first data element from the new burst follows either the last element of a
completed burst or the last desired data element of a longer burst which is being trun-
cated. The new READ command should be issued x cycles after the first READ
command, where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture). This is shown in Figure 11 on page 23.
A READ command can be initiated on any clock cycle following a previous READ
command. Nonconsecutive read data is shown for illustration in Figure 12 on page 24.
Full-speed random read accesses within a page (or pages) can be performed, as shown
in Figure 13 on page 25.
NOP
T1
t
t
RRD
RCD (
t
DQSCK (DQS transition skew to CK) and
t
NOP
RRD) MIN When 2 <
T2
Bank y
Row
ACT
20
T3
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (
t
DQSQ (valid data-out skew),
NOP
T4
t
RRD) MIN/
t RCD
NOP
T5
t
AC (data-out transition skew to
t
CK ≤ 3
©2004 Micron Technology, Inc. All rights reserved.
RD/WR
Bank y
T6
Col
t
QH (data-out
Operations
DON’T CARE
T7
NOP