MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 15

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 6:
Table 7:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank)
or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER (standard or extended mode
registers)
Truth Table – Commands
Note 1 applies to all commands; All states and sequences not shown are reserved and/or illegal.
Truth Table – DM Operation
Notes:
Name (Function)
Note:
Table 6 and Table 7 provide quick references of available commands. This is followed by
a written description of each command. Three additional Truth Tables (Table 8 on
page 42, Table 9 on page 43, and Table 10 on page 45) provide CKE commands and
current/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0–BA1 select either the standard mode register or the extended mode register
3. BA0–BA1 provide bank address and A0–A11 provide row address.
4. BA0–BA1 provide bank address; A0–A8 provide column address; A10 HIGH enables the auto
5. A10 LOW: BA0–BA1 determine which bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
8. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
9. DESELECT and NOP are functionally interchangeable.
Name (Function)
Write enable
Write inhibit
(BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 1, BA1 = 0 select extended mode
register; other combinations of BA0–BA1 are reserved). A0–A11 provide the op-code to be
written to the selected mode register.
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
for CKE.
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
Used to mask write data; provided coincident with corresponding data.
15
CS#
H
L
L
L
L
L
L
L
L
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
H
H
H
H
X
L
L
L
L
DM
CAS#
H
L
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2004 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
Valid
Commands
DQ
X
Notes
6, 7
9
9
3
4
4
8
5
2