IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 12

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1. PLCC, TQFP and STQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. t
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. 'X' in part numbers indicates power rating (S or L).
BUSY TIMING (For MASTER IDT 7130)
t
t
t
t
t
t
t
t
t
BUSY INPUT TIMING (For SLAVE IDT 7140)
t
t
t
t
BUSY TIMING (For MASTER IDT 7130)
t
t
t
t
t
t
t
t
t
BUSY INPUT TIMING (For SLAVE IDT 7140)
t
t
t
t
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
WB
WH
WDD
DDD
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
WB
WH
WDD
DDD
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Symbol
Symbol
BDD
is a calculated parameter and is the greater of 0, t
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
BUSY Access Time from Address]
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
(5)
(5)
(6)
(6)
(6)
(6)
(2)
(2)
(2)
(2)
(4)
(4)
(3)
(3)
Parameter
(2)
(2)
(2)
(2)
WDD
Parameter
– t
WP
(actual) or t
DDD
12
– t
DW
(actual).
Military, Industrial and Commercial Temperature Ranges
Min.
____
____
____
____
____
____
____
____
____
12
12
5
0
Com'l Only
7130X20
7140X20
Max.
(1)
(1)
____
____
____
____
20
20
20
20
40
30
25
40
30
(7)
Min.
Min.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
15
15
20
20
5
0
5
0
Com'l, Ind
& Military
Com'l, Ind
& Military
7130X25
7140X25
7130X55
7140X55
Max.
Max.
____
____
____
____
20
20
20
20
50
35
35
50
35
____
____
____
____
30
30
30
30
80
55
55
80
55
Min.
Min.
____
____
____
____
____
____
____
____
____
20
20
____
____
____
____
____
____
____
____
____
20
20
5
0
5
0
& Military
Com'l, Ind
& Military
7130X100
7140X100
7130X35
7140X35
Com'l
Max.
Max.
____
____
____
____
120
100
120
100
20
20
20
20
60
35
35
60
35
____
____
____
____
50
50
50
50
65
2689 tbl 11a
2689 tbl 11b
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns