IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 10

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but
2. PLCC, TQFP and STQFP packages only.
3. For MASTER/SLAVE combination, t
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
5. 'X' in part numbers indicates power rating (SA or LA).
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
is not production tested.
to be placed on the bus for the required t
can be as short as the specified t
Symbol
Symbol
Chip Enable to End-of-Write
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
Output Active from End-of-Write
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High-Z
Chip Enable to End-of-Write
Data Valid to End-of-Write
Output High-Z Time
Data Hold Time
Output Active from End-of-Write
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High-Z
WP
(3)
(3)
(4)
(4)
(1)
.
WC
(1)
= t
DW
BAA
Parameter
. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse
+ t
WP
(1)
(1)
(1)
(1)
, since R/W = V
Parameter
IL
must occur after t
10
BAA.
Min.
____
____
20
15
15
15
10
0
0
0
0
Com'l Only
Military, Industrial and Commercial Temperature Ranges
7130X20
7140X20
WP
or (t
Max.
WZ
(2)
(2)
____
____
____
____
____
____
____
____
____
10
10
+ t
(5)
DW
) to allow the I/O drivers to turn off data
Min.
Min.
____
____
25
20
20
15
12
____
____
55
40
40
30
20
0
0
0
0
0
0
0
0
Com'l, Ind
& Military
Com'l, Ind
& Military
7130X25
7140X25
7130X55
7140X55
Max.
Max.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
10
10
25
25
Min.
Min.
____
____
100
35
30
30
25
____
____
15
90
90
55
40
0
0
0
0
0
0
0
0
& Military
Com'l, Ind
& Military
7130X100
7140X100
7130X35
7140X35
Com'l
Max.
Max.
____
____
____
____
____
____
____
____
____
15
15
____
____
____
____
____
____
____
____
____
40
40
2689 tbl 10a
2689 tbl 10b
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns