IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 11

• Manufacturer Part Number: IDT7130SA55P
• Description: IC SRAM 8KBIT 55NS 48DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: -r

Specifications of IDT7130SA55P

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 8K (1K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-DIP
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 48
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 7130SA55P

ADDRESS
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
DATA
ADDRESS
DATA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
DATA
(Figure 2).
bus for the required t
WR
R/W
is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
OUT
R/W
OE
CE
CE
IN
IN
DW
. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
t
EW
AS
t
AS
or t
(6)
(6)
WP
(4)
) of CE = V
IL
and R/W = V
t
WZ
(7)
t
AW
t
IL.
AW
t
WC
t
t
WC
WP
t
EW
11
(2)
(2)
Military, Industrial and Commercial Temperature Ranges
t
DW
WP
or (t
t
DW
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
t
WR
(3)
t
WR
t
(3)
t
DH
OW
t
DH
t
HZ
(1,5)
(1,5,8)
(7)
t
HZ
(4)
(7)
2689 drw 11
2689 drw 10
WP
.