IDT7130SA55P IDT, Integrated Device Technology Inc, IDT7130SA55P Datasheet - Page 13

no-image

IDT7130SA55P

Manufacturer Part Number
IDT7130SA55P
Description
IC SRAM 8KBIT 55NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Series
-r
Datasheets

Specifications of IDT7130SA55P

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
48
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130SA55P

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT7130SA55P
Manufacturer:
IDT
Quantity:
1 169
Part Number:
IDT7130SA55P
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT7130SA55PB
Manufacturer:
IDT
Quantity:
1 169
Part Number:
IDT7130SA55PF
Manufacturer:
HIROSE ELECTRIC
Quantity:
4
Part Number:
IDT7130SA55PF
Manufacturer:
IDT
Quantity:
300
Part Number:
IDT7130SA55PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7130SA55PF
Manufacturer:
IDT
Quantity:
242
Part Number:
IDT7130SA55PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
DATA
Timing Waveform of Write with Port-to-Port Read and BUSY
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
DATA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
ADDR
BUSY
WH
ADDR
R/ W
OUT"B"
L
must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
= CE
IN"A"
"B"
"B"
"A "
IL
"A"
for the reading port.
R
= V
IL
BUSY
R/W
R/W
"B"
"B"
"A"
t
APS
(1)
"B"
, until BUSY
BDD
is ignored for slave (IDT7140).
"B"
t
goes HIGH.
BAA
t
WB
MATCH
t
WC
13
(2)
t
WP
(3)
t
WP
Military, Industrial and Commercial Temperature Ranges
MATCH
t
VALID
DW
t
BDA
t
WDD
t
WH
(1)
t
DDD
2689 drw 13
t
DH
t
BDD
(2,3,4)
,
VALID
2689 drw 12

Related parts for IDT7130SA55P