M34E02-FDW1TP STMicroelectronics, M34E02-FDW1TP Datasheet - Page 32

• Manufacturer Part Number: M34E02-FDW1TP
• Description: IC EEPROM 2KBIT 400KHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M34E02-FDW1TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-TSSOP
• Organization: 256 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 1.7 V, 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8654-2; M34E02-FDW1TP

Revision history
10
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Revision history
Table 18.
13-Nov-2003
01-Dec-2003
29-Mar-2004
14-Apr-2004
24-Nov-2004
11-Mar-2005
28 -Apr-2005
10-Apr-2006
Date
Document revision history
Revision
1.0
1.1
1.2
2.0
3.0
4.0
5.0
6
First release
TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package.
Correction to sentence in “Setting the Write Protection”. Correction to
specification of t
Always NoACK after Address and Data bytes in
V
test condition of V
Soldering temperature information clarified for RoHS compliant devices.
First public release
Direct connection of E0, E1, E2 to V
E1, E2)
and Z
removed from the Parameter descriptions of V
characteristics (for temperature range 6
Document status promoted from Product Preview to full Datasheet.
Datasheet title changed.
Plating Technology options updated in
scheme.
Resistance and capacitance renamed in
versus bus parasitic capacitance (C) for an I2C
Text in
parameters
DC characteristics (for temperature range 6
In
400kHz, related AC timings (t
t
Power On Reset paragraph removed replaced by
Figure 3: Device select code
characteristics (for temperature range 6
Note
All packages are ECOPACK® (see text added under
numbering, T
CHDH
IO
Table 14: AC
and V
3
EiH
, t
Doc ID 10367 Rev 9
Power On Reset
added to
DHDL
and
parameters added to
CC
modified. I
Use within a DDR1/DDR2 DRAM module
) also modified.
(min) in Absolute Maximum Ratings table. I
LEAD
characteristics: Frequency f
NS
Figure 14
OL
removed from
values.
. MLP package mechanical data respecified.
CC
changed. Noise filter value in
Features
value 2mA, when Vcc=3/6V, added to
and Note
CHCL
inserted. I
Table 11: Input
Changes
Table 7: Absolute maximum
, t
revised.
CLCH
SS
2
added to
Table 17: Ordering information
and V
CC1
devices).
devices).
, t
Figure 4: Maximum RP value
DXCX
modified in
C
devices).
CC
changed from 100kHz to
IL
parameters. E0, E1, E2
, t
bus.
Table
Figure 15
and V
(see
CLQV
Internal device
Description
Chip Enable (E0,
Table 11: Input
6. Improvement in
IH
paragraphs). Z
max, t
Table 13: DC
OL
in
Table 13: DC
changed for
CHDX
ratings).
Table 13:
and
M34E02
reset.
, t
DLCL
Part
EiL
,