M34E02-FMC6TG STMicroelectronics, M34E02-FMC6TG Datasheet
M34E02-FMC6TG
Specifications of M34E02-FMC6TG
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M34E02-FMC6TG Summary of contents
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... More than 40 years’ data retention ® ■ ECOPACK (RoHS compliant) packages ■ Packages: ® – ECOPACK2 (RoHS-compliant and Halogen-free) May 2011 2 Kbit serial presence detect (SPD) EEPROM Doc ID 10367 Rev 11 M34E02 M34E02-F UFDFPN8 ( TSSOP8 (DW) 4.4 × www.st.com 1/34 1 ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 10367 Rev 11 M34E02, M34E02-F ...
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... M34E02, M34E02-F 5 Use within a DDR1/DDR2 DRAM module . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Programming the M34E02 and M34E02 5.1.1 5.1.2 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Isolated DRAM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DRAM module inserted in the application motherboard . . . . . . . . . . . . 19 Doc ID 10367 Rev 11 ...
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... Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4/34 Doc ID 10367 Rev 11 M34E02, M34E02-F ...
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... M34E02, M34E02-F List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TSSOP and MLP connections (top view Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Maximum R value versus bus parasitic capacitance (C) for Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Result of setting the write protection Figure 7. Setting the write protection ( Figure 8. ...
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... Description The M34E02 and M34E02-F are 2 Kbit serial EEPROM memories able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD). ...
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... M34E02, M34E02-F Figure 2. TSSOP and MLP connections (top view) 1. See the Package mechanical data Table 1. Signal names Signal names E0, E1, E2 SDA SCL section for package dimensions, and how to identify pin-1. Description Chip Enable Serial Data Serial Clock Write Control Supply voltage ...
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... When Write Control (WC) is tied low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register. 8/34 indicates how the value of the pull-up resistor can be calculated). In voltage, when decoding an SWP or CWP instruction. HV Doc ID 10367 Rev 11 M34E02, M34E02-F . (Figure 4 indicates how ...
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... M34E02, M34E02-F 2.5 Supply voltage (V 2.5.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V secure a stable DC supply voltage recommended to decouple the V suitable capacitor (usually of the order 100 nF) close to the V pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t 2 ...
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... E0, E1 and E2 are compared against the respective external pins on the memory device defined in HV 10/34 SDA SDA Start Input Change condition MSB MSB Device type identifier Chip Enable signals ( ( ( ( Table 13. Doc ID 10367 Rev 11 M34E02, M34E02-F Stop condition ACK ACK condition Chip Enable bits Stop AI00792c ...
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... M34E02, M34E02-F 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Standard Array 00h Default EEPROM memory area state before write access to the Protect Register Doc ID 10367 Rev 11 M34E02, M34E02 bus. Each one is given a th bit time. If the device does not match Initial Sequence Start, Device Select Start, Device Select Address ...
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... This write-protection cannot be cleared by any instruction power-cycling the device, and regardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the M34E02 and M34E02-F no longer acknowledge any instruction (with a device type identifier of 0110) to access the write-protection settings. Figure 7. ...
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... NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 14/34 Figure 8, and waits for an address byte. Figure 8 Doc ID 10367 Rev 11 M34E02, M34E02-F ...
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... M34E02, M34E02-F Figure 8. Write mode sequences in a non write-protected area Byte Write Page Write Figure 9. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device ReStart ACK Device select Byte address R/W ACK Device select Byte address ...
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... The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 16/34 Figure 9, is: Figure 10. Doc ID 10367 Rev 11 M34E02, M34E02 ...
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... M34E02, M34E02-F 3.8.4 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. ...
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... Programming the M34E02 and M34E02-F The situations in which the M34E02 and M34E02-F are programmed can be considered under two headings: ● when the DDR2 DRAM is isolated (not inserted on the PCB motherboard) ● when the DDR2 DRAM is inserted on the PCB motherboard 5.1.1 ...
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... M34E02, M34E02-F 5.1.2 DRAM module inserted in the application motherboard As the final application cannot drive the E0 pin to V the write-protection with the PSWP instruction. Table 5 and Table 6 status. Table 5. Acknowledge when writing data or defining the write-protection (instructions with R/W bit = 0) WC Status ...
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... NoAck Not significant SWP NoAck Not significant CWP Ack Not significant PSWP Ack Not significant Ack Not significant Doc ID 10367 Rev 11 M34E02, M34E02-F Ack Data byte Ack NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant ...
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... M34E02, M34E02-F Figure 11. Serial presence detect block diagram DRAM module slot number 7 DRAM module slot number 6 DRAM module slot number 5 DRAM module slot number 4 DRAM module slot number 3 DRAM module slot number 2 DRAM module slot number 1 DRAM module slot number 0 1. E0, E1 and E2 are wired at each DRAM module slot in a binary sequence for a maximum of 8 devices. ...
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... DC output current (SDA = Supply voltage CC V Electrostatic discharge voltage (human body model) ESD 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 22/34 Parameter E0 Others (1) Doc ID 10367 Rev 11 M34E02, M34E02-F Min. Max. Unit –55 130 °C –65 150 °C –0.50 10.0 V –0.50 6.5 ...
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... M34E02, M34E02 and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Device not selected Device not selected 2.5 ≤ V 1.7 V ≤ – 2.1 mA, 2.2 V ≤ 0.7 mA triggered by the correct decoding of a write command Doc ID 10367 Rev 11 M34E02, M34E02-F Min. Max < 0. > 0.7V 800 CC < 0. > 0.7V 500 CC 100 Min Max Table 100 kHz ...
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... M34E02, M34E02-F Table 13. DC characteristics (for temperature range 6 devices) Symbol Parameter Input leakage current I LI (SCL, SDA) I Output leakage current LO I Supply current (read Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) Input high voltage V IH (SCL, SDA, WC) ...
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... Start condition setup time Start condition hold time Stop condition setup time Time between Stop condition and next Start condition Write time × C time constant is within the values specified in bus bus Doc ID 10367 Rev 11 M34E02, M34E02-F 10, Table 8 and Table 9 Min. Max. 400 600 1300 20 ...
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... M34E02, M34E02-F Figure 13. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL tXH1XH2 Start condition SCL SDA In tCHDH Stop condition tCHCL SCL tCLQV SDA Out tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle tCLQX Data valid Data valid Doc ID 10367 Rev 11 ...
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... Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. 28/34 Doc ID 10367 Rev 11 M34E02, M34E02-F ® ...
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... M34E02, M34E02-F Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline 1. Drawing is not to scale. 2. The central pad (area the above illustration) is pulled, internally connected to any other voltage or signal line on the PCB, for example during the soldering process. ...
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... Doc ID 10367 Rev 11 M34E02, M34E02-F c α TSSOP8AM (1) inches Typ. Min. Max. 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 ...
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... M34E02, M34E02-F 9 Part numbering Table 17. Ordering information scheme Example: Device type 2 M34 = ASSP I C serial access EEPROM Device function E02 = 2 Kbit (256 × 8) SPD (serial presence detect) for DDR1 and DDR2 Operating voltage 1.7 to 3.6 V over 0° ° 1.7 to 5.5 V over –40 ° °C ...
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... Figure 3: Device select code characteristics (for temperature range 6 Note 3 added to Figure 14 All packages are ECOPACK® (see text added under numbering, T removed from LEAD Doc ID 10367 Rev 11 M34E02, M34E02-F Changes Table 6. Improvement in OL and V (see Chip Enable (E0 paragraphs). Z Table 11: Input parameters. E0, E1, E2 ...
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... Table 13: DC characteristics (for temperature range 6 devices) 9 Updated Figure 14: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline lead ultra thin fine pitch dual flat package no lead mm, data Added M34E02-F part number. Added ambient temperature with power applied in maximum ratings. Updated I conditions in CC1 range 1 devices) ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 34/34 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 10367 Rev 11 M34E02, M34E02-F ...