M34E02-FDW1TP STMicroelectronics, M34E02-FDW1TP Datasheet
M34E02-FDW1TP
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M34E02-FDW1TP
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M34E02-FDW1TP Summary of contents
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... More than 40 years’ data retention ® ■ ECOPACK (RoHS compliant) packages ■ Packages: ® – ECOPACK2 (RoHS-compliant and Halogen-free) April 2010 2 Kbit serial presence detect (SPD) EEPROM Doc ID 10367 Rev 9 M34E02 UFDFPN8 (MB or MC) 2 × (MLP) TSSOP8 (DW) 4.4 × 1/34 www.st.com 1 ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 10367 Rev 9 M34E02 ...
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... M34E02 5 Use within a DDR1/DDR2 DRAM module . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 5.1.2 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Isolated DRAM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DRAM module inserted in the application motherboard . . . . . . . . . . . . 19 Doc ID 10367 Rev 9 Contents 3/34 ...
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... DC characteristics (for temperature range 6 devices Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4/34 Doc ID 10367 Rev 9 M34E02 ...
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... M34E02 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TSSOP and MLP connections (top view Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Maximum R value versus bus parasitic capacitance (C) for Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Result of setting the write protection Figure 7. Setting the write protection ( Figure 8. Write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 ...
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... Description 1 Description The M34E02 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with serial presence detect (SPD). All the ...
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... M34E02 Figure 2. TSSOP and MLP connections (top view) 1. See the Package mechanical data Table 1. Signal names Signal names E0, E1, E2 SDA SCL M34E02 SCL SDA AI09021 section for package dimensions, and how to identify pin-1. Description Chip Enable Serial Data Serial Clock Write Control ...
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... When Write Control (WC) is tied low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register. 8/34 indicates how the value of the pull-up resistor can be calculated). In voltage, when decoding an SWP or CWP instruction M34E02 M34E02 Doc ID 10367 Rev 9 M34E02 . (Figure 4 indicates how Ai12301 to ...
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... M34E02 2.5 Supply voltage (V 2.5.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V secure a stable DC supply voltage recommended to decouple the V suitable capacitor (usually of the order 100 nF) close to the V pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t 2 ...
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... E0, E1 and E2 are compared against the respective external pins on the memory device defined in HV 10/34 SDA SDA Start Input Change condition MSB MSB Device type identifier Chip Enable signals ( ( ( ( Table 13. Doc ID 10367 Rev 9 Stop condition ACK ACK condition Chip Enable bits M34E02 Stop AI00792c ...
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... M34E02 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Start, Device Select Start, Device Select Address reStart, Device Select Similar to Current or Random Address Read Start, Device Select Start, Device Select FFh Standard Array 80h 7Fh Write Protected Array 00h State of the EEPROM memory area after write access to the Protect Register AI01936C M34E02 ...
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... This write-protection cannot be cleared by any instruction power-cycling the device, and regardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the M34E02 no longer acknowledges any instruction (with a device type identifier of 0110) to access the write-protection settings ...
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... NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 14/34 Figure 8, and waits for an address byte. Figure 8 Doc ID 10367 Rev 9 M34E02 ...
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... M34E02 Figure 8. Write mode sequences in a non write-protected area Byte Write Page Write Figure 9. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device ReStart ACK Device select Byte address R/W ACK Device select Byte address R/W ...
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... The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 16/34 Figure 9, is: Figure 10. Doc ID 10367 Rev 9 M34E02 ) is w ...
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... M34E02 3.8.4 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. ...
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... The device is delivered with all bits in the memory array set to ‘1’ (each Byte contains FFh). 5 Use within a DDR1/DDR2 DRAM module In the application, the M34E02 is soldered directly in the printed circuit module. The three Chip Enable inputs (E0, E1, E2) must be connected to V using a pull-up or pull-down resistor) through the DIMM socket (see ...
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... M34E02 5.1.2 DRAM module inserted in the application motherboard As the final application cannot drive the E0 pin to V the write-protection with the PSWP instruction. Table 5 and Table 6 status. Table 5. Acknowledge when writing data or defining the write-protection (instructions with R/W bit = 0) WC Status input ...
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... NoAck Not significant SWP NoAck Not significant CWP Ack Not significant PSWP Ack Not significant Ack Not significant Doc ID 10367 Rev 9 M34E02 Ack Data byte Ack NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant NoAck NoAck Not significant ...
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... M34E02 Figure 11. Serial presence detect block diagram DRAM module slot number 7 DRAM module slot number 6 DRAM module slot number 5 DRAM module slot number 4 DRAM module slot number 3 DRAM module slot number 2 DRAM module slot number 1 DRAM module slot number 0 1. E0, E1 and E2 are wired at each DRAM module slot in a binary sequence for a maximum of 8 devices. ...
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... Input or output range output current (SDA = Supply voltage CC V Electrostatic discharge voltage (human body model) ESD 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 22/34 Parameter E0 Others (1) Doc ID 10367 Rev 9 M34E02 Min. Max. Unit –65 150 °C –0.50 10.0 V –0.50 6 –0.5 6.5 V – ...
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... M34E02 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... CC < 0. > 0.7V 500 CC 100 Min Max Table 100 kHz c = 100 kHz 3 1 –0.45 0 < 2.5 V –0.45 0.25V CC 0. 4 M34E02 Unit pF pF k k k k ns Unit ± 2 µA ± 2 µ µA 1 µ 0.4 V 0.2 V ...
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... M34E02 Table 13. DC characteristics (for temperature range 6 devices) Symbol Parameter Input leakage current I LI (SCL, SDA) I Output leakage current LO I Supply current (read Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) Input high voltage V IH (SCL, SDA, WC high voltage ...
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... Start condition hold time Stop condition setup time Time between Stop condition and next Start condition Write time Doc ID 10367 Rev 9 10, Table 8 and Table 9 Min. Max. 400 600 1300 20 100 20 300 20 300 100 0 200 200 900 600 600 600 1300 5 M34E02 Unit kHz ...
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... M34E02 Figure 13. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX tXH1XH2 Start condition SCL SDA In tCHDH Stop condition tCHCL SCL tCLQV SDA Out tCHCL tCLCH tCLDX tDXCX SDA Change SDA Input tW Write cycle tCLQX Data valid Data valid Doc ID 10367 Rev 9 ...
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... Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. 28/34 Doc ID 10367 Rev 9 M34E02 ® ...
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... M34E02 Figure 14. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline Drawing is not to scale. 2. The central pad (the area the above illustration) is pulled, internally allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process ...
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... Doc ID 10367 Rev 9 M34E02 TSSOP8AM (1) inches Typ. Min. Max. 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 0.1181 ...
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... The 1.7 to 3.6 V operating voltage range is available only on temperature range 1 devices. 2. The 1.7 to 5.5 V operating voltage range is available only on temperature range 6 devices. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. M34E02 (1) or (2) ...
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... Vcc=3/6V, added to devices). changed from 100kHz max, t CHCL CLCH DXCX CLQV Internal device inserted. I modified in Table 13: DC CC1 devices). and Note 2 added to Figure 15 Description Table 7: Absolute maximum M34E02 changed for EiL Table 13: DC Table 13 CHDX DLCL reset. and Part ratings). ...
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... M34E02 Table 18. Document revision history (continued) Date Revision 18-Mar-2009 25-Sep-2009 01-Apr-2010 Datasheet title and Features on page 1 with DDR1 and DDR2 DRAM configurations. Temperature range 6 added, operating voltage range V device temperature range 6. I Absolute maximum ratings and V modified range 6 devices). Table 14: AC characteristics ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 34/34 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 10367 Rev 9 M34E02 ...