Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 93
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Z8F011ASH020EG2156
Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F011AHJ020EG2156.pdf
(257 pages)
Specifications of Z8F011ASH020EG2156
Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS025113-1212
PWM Period (s)
If an initial starting value other than
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is repre-
sented by:
PWM Output High Time Ratio (%)
If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is repre-
sented by:
PWM Output High Time Ratio (%)
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic
PWM signal and its complement) through two GPIO port pins. The timer input is the sys-
tem clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM
High and Low Byte registers. When the timer count value matches the PWM value, the
timer output toggles. The timer continues counting until it reaches the reload value stored
in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to
If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
timer output signal returns to a High (1) after the timer reaches the reload value and is
reset to
If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
timer output signal returns to a Low (0) after the timer reaches the reload value and is reset
to
The timer also generates a second PWM output signal: the timer output complement. The
timer output complement is the complement of the timer output PWM signal. A program-
mable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a Low to a High (inactive to active) to
ensure a time gap between the deassertion of one PWM output to the assertion of its com-
plement.
0001H
0001H
0001H
.
.
and counting resumes.
=
------------------------------------------------------------------------
System Clock Frequency (Hz)
Reload Value Prescale
0001H
=
=
Reload Value PWM Value
-------------------------------------------------------------------- -
--------------------------------
Reload Value
PWM Value
is loaded into the Timer High and Low Byte
Reload Value
–
100
Z8 Encore!
Product Specification
100
®
F0830 Series
Operation
75
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