Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 78

• Manufacturer Part Number: Z8F011ASH020EG2156
• Description: 8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F011ASH020EG2156

• Rohs: yes
• Core: eZ8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 1 KB
• Data Ram Size: 256 B
• On-chip Adc: No
• Package / Case: SOIC-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS025113-1212
Bit
Field
RESET
R/W
Address
Bit
[7:4]
[3]
PCxI
Note: x indicates the specific GPIO port pin number (3–0).
Interrupt Request 2 Register
IRQ0 Enable High and Low Bit Registers
Description
Reserved
These registers are reserved and must be programmed to 0000.
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
R/W
7
0
The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for
both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the
corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
Table 38 lists the priority control values for IRQ0. The IRQ0 Enable High and Low Bit
registers, shown in Tables 39 and 40, form a priority-encoded enabling service for inter-
rupts in the Interrupt Request 0 Register. Priority is generated by setting the bits in each
register.
IRQ0ENH[x]
Note: x indicates the register bits in the range 7–0.
R/W
0
0
1
1
6
0
Table 37. Interrupt Request 2 Register (IRQ2)
Table 38. IRQ0 Enable and Priority Encoding
Reserved
IRQ0ENL[x]
R/W
5
0
0
1
0
1
R/W
4
0
FC6H
Disabled
Priority
Level 1
Level 2
Level 3
PC3I
R/W
3
0
Interrupt Control Register Definitions
Description
Disabled
Nominal
PC2I
R/W
High
Low
Z8 Encore!
2
0
Product Specification
PC1I
R/W
1
0
®
F0830 Series
PC0I
R/W
0
0
60