Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 167

• Manufacturer Part Number: Z8F011ASH020EG2156
• Description: 8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F011ASH020EG2156

• Rohs: yes
• Core: eZ8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 1 KB
• Data Ram Size: 256 B
• On-chip Adc: No
• Package / Case: SOIC-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS025113-1212
Bit
Field
RESET
R/W
Bit
[7]
DBGMODE
[6]
BRKEN
[5]
DBGACK
[4:1]
[0]
RST
DBGMODE
Description
DEBUG Mode
The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and breakpoints are enabled. If the
Flash read protect option bit is enabled, this bit can only be cleared by resetting the device. It
cannot be written to 0.
0 = The Z8 Encore! F0830 Series device is operating in NORMAL Mode.
1 = The Z8 Encore! F0830 Series device is in DEBUG Mode.
Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug acknowledge character (FFH) to the host when a breakpoint occurs.
0 = Debug acknowledge is disabled.
1 = Debug acknowledge is enabled.
Reserved
These bits are reserved and must be programmed to 0000.
Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of the reset sequence.
0 = No effect.
1 = Reset the Flash read protect option bit device.
R/W
7
0
BRKEN
R/W
6
0
Table 96. OCD Control Register (OCDCTL)
DBGACK
R/W
5
0
R
4
0
On-Chip Debugger Control Register Definitions
R
3
0
Reserved
Z8 Encore!
R
2
0
Product Specification
R
1
0
®
F0830 Series
RST
R/W
0
0
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