Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 97

• Manufacturer Part Number: Z8F011ASH020EG2156
• Description: 8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F011ASH020EG2156

• Rohs: yes
• Core: eZ8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 1 KB
• Data Ram Size: 256 B
• On-chip Adc: No
• Package / Case: SOIC-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS025113-1212
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the timer PWM High and Low Byte registers to
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time between the timer start and the capture event can be
calculated using the following equation:
Capture Elapsed Time (s)
COMPARE Mode
In COMPARE Mode, the timer counts up to 16-bit maximum compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to
enabled, the timer output pin changes state (from Low to High or from High to Low) upon
compare.
If the timer reaches
Observe the following steps for configuring a timer for COMPARE Mode and for initiat-
ing the count:
1. Write to the Timer Control Register to:
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
ware to determine if interrupts are generated by either a capture event or a reload. If
the PWM High and Low Byte registers still contain
interrupt were generated by a reload.
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. The user can configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting the TICONFIG
field of the TxCTL1 Register.
–
–
–
–
Disable the timer
Configure the timer for COMPARE Mode
Set the prescale value
Set the initial logic level (High or Low) for the timer output alternate function
FFFFH
0001H
, the timer resets to
=

-------------------------------------------------------------------------------------------------- -
Capture Value Start Value
). Additionally, if the timer output alternate function is
System Clock Frequency (Hz)
–
0000H
and continues counting.
0000H
0000H
 Prescale
Z8 Encore!

after the interrupt, the
Product Specification
. This allows user soft-
®
F0830 Series
Operation
79