Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 161
Z8F011ASH020EG2156
Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F011AHJ020EG2156.pdf
(257 pages)
Specifications of Z8F011ASH020EG2156
Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS025113-1212
OCD Serial Errors
Breakpoints
If the OCD receives a serial break (nine or more continuous bits low), the autobaud detec-
tor/generator resets. Reconfigure the autobaud detector/generator by sending
The OCD can detect any of the following error conditions on the DBG pin:
•
•
•
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long serial break back to the host and resets the autobaud detec-
tor/generator. A framing error or transmit collision may be caused by the host sending a
serial break to the OCD. As a result of the open-drain nature of the interface, returning a
serial break back to the host only extends the length of the serial break if the host releases
the serial break early.
The host transmits a serial break on the
F0830 Series devices or when recovering from an error. A serial break from the host resets
the autobaud generator/detector, but does not reset the OCD Control Register. A serial
break leaves the device in DEBUG Mode, if that is the current mode. The OCD is held in
reset until the end of the serial break when the DBG pin returns high. Because of the open-
drain nature of the DBG pin, the host can send a serial break to the OCD even if the OCD
is transmitting a character.
Execution breakpoints are generated using the
eZ8 CPU decodes a BRK instruction, it signals the OCD. If breakpoints are enabled, the
OCD enters DEBUG Mode and idles the eZ8 CPU. If breakpoints are not enabled, the
OCD ignores the BRK signal and the
Breakpoints in Flash Memory
The
byte in Flash memory. To implement a breakpoint, write
overwriting the current instruction. To remove a breakpoint, the corresponding page of
Flash memory must be erased and reprogrammed with the original data.
Serial break (a minimum of nine continuous bits Low)
Framing error (received Stop bit is Low)
Transmit collision (simultaneous transmission by OCD and host detected by the OCD)
BRK
instruction is opcode
00H
, which corresponds to the fully programmed state of a
BRK
DBG
instruction operates as an NOP instruction.
pin when first connecting to the Z8 Encore!
BRK
instruction (opcode
00H
Z8 Encore!
to the required break address
Product Specification
00H
®
F0830 Series
). When the
80H
Operation
.
143
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