Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 46
Z8F011ASH020EG2156
Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F011AHJ020EG2156.pdf
(257 pages)
Specifications of Z8F011ASH020EG2156
Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS025113-1212
Debug Pin Driven Low
Reset Register Definitions
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin
is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin,
the low pulse must be greater than the minimum width specified about 12 ns or it is
ignored. The EXT bit in the Reset Status (RSTSTAT) Register is set.
Debug reset is initiated when the On-Chip Debugger detects any of the following error
conditions on the DBG pin:
•
•
•
When the Z8F0830 Series device is operating in STOP Mode, the debug reset will cause a
system reset. The On-Chip Debugger block is not reset, but the remainder of the chip’s
operations go through a normal system reset. The POR bit in the Reset Status (RSTSTAT)
Register is set to 1.
The following sections define the Reset registers.
Reset Status Register
The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indi-
cates the source of the most recent Reset event, Stop Mode Recovery event or Watchdog
Timer time-out event. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer Control Register, which is write-
only.
Serial break (a minimum of nine continuous bits Low)
Framing error (received STOP bit is Low)
Transmit collision (simultaneous OCD and host transmission detected by the OCD)
Z8 Encore!
Product Specification
Debug Pin Driven Low
®
F0830 Series
28
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