Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 45

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Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS025113-1212
Operating
Mode
STOP Mode
Caution:
Stop Mode Recovery using WDT Time-Out
Stop Mode Recovery using GPIO Port Pin Transition
The eZ8 CPU fetches the reset vector at program memory addresses
and loads that value into the program counter. Program execution begins at the reset vector
address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions.
The following sections provide more details about each of the Stop Mode Recovery
sources.
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! F0830 Series device is configured to respond to interrupts, the eZ8 CPU
services the WDT interrupt request following the normal Stop Mode Recovery sequence.
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. If
any GPIO pin is enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. In the Reset Sta-
tus (RSTSTAT) Register, the STOP bit is set to 1.
Stop Mode Recovery Source
Watchdog Timer time-out when configured
for Reset
Watchdog Timer time-out when configured
for interrupt
Data transition on any GPIO port pin enabled
as a Stop Mode Recovery source
Assertion of external RESET Pin
Debug pin driven Low
In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. These Port Input
Data registers record the port transition only if the signal stays on the port pin through the
end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
Table 11. Stop Mode Recovery Sources and Resulting Action
Action
Stop Mode Recovery
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Stop Mode Recovery
System reset
System reset
Z8 Encore!
Product Specification
0002H
Stop Mode Recovery
®
F0830 Series
and
0003H
27

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