C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 68
C8051T622-GMR
Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet
1.C8051T622-GMR.pdf
(254 pages)
Specifications of C8051T622-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051T622/3 and C8051T326/7
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
SFR Address = 0xF7
68
Name
Reset
7:4
Bit
Type
3
2
1
0
Bit
Reserved Reserved. Must Write 0b.
Unused
PVBUS
Name
PMAT
PS1
R
7
0
Unused. Read = 0000b, Write = Don't Care.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
R
6
0
R
5
0
Rev. 1.1
R
4
0
Function
PMAT
R/W
3
0
Reserved
R/W
2
0
PS1
R/W
1
0
PVBUS
R/W
0
0
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