C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 112

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C8051T622-GMR

Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051T622-GMR

Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T622-GMR
Manufacturer:
SILICON
Quantity:
5 000
C8051T622/3 and C8051T326/7
SFR Definition 17.11. P0SKIP: Port 0 Skip
SFR Address = 0xD4
SFR Definition 17.12. P1: Port 1
SFR Address = 0x90; Bit-Addressable
112
Name
Reset
Name
Reset
7:0
6:0
Bit
Bit
Type
Type
7
Bit
Bit
Unused
P0SKIP[7:0]
P1[6:0]
Name
Name
R
7
0
7
1
Unused. Read = 1b. Write = don’t care.
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
Rev. 1.1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P0SKIP[7:0]
R/W
P1[6:0]
Function
Write
R/W
3
0
3
1
2
0
2
1
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1

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