C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 120

• Manufacturer Part Number: C8051T622-GMR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
• Manufacturer: Silicon Labs

Specifications of C8051T622-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051T622/3 and C8051T326/7
SFR Definition 18.2. USB0ADR: USB0 Indirect Address
SFR Address = 0x96
120
Name
Reset
5:0 USBADDR[5:0] USB0 Indirect Register Address Bits.
Bit
Type
7
6
Bit
AUTORD
BUSY
Name
BUSY
R/W
7
0
AUTORD
USB0 Register Read
Busy Flag.
This bit is used during
indirect
accesses.
USB0 Register Auto-read Flag.
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software
reads USB0DAT (USBADDR bits will not be changed).
These bits hold a 6-bit address used to indirectly access the USB0 core registers.
Table 18.2 lists the USB0 core registers and their indirect addresses. Reads and
writes to USB0DAT will target the register indicated by the USBADDR bits.
R/W
6
0
Description
USB0
5
0
register
Rev. 1.1
4
0
0: No effect.
1: A USB0 indirect regis-
ter read is initiated at the
address specified by the
USBADDR bits.
USBADDR[5:0]
Write
3
0
R/W
2
0
0: USB0DAT register data
is valid.
1: USB0 is busy access-
ing an indirect register;
USB0DAT register data is
invalid.
1
0
Read
0
0