C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 140
C8051T622-GMR
Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet
1.C8051T622-GMR.pdf
(254 pages)
Specifications of C8051T622-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051T622/3 and C8051T326/7
USB Register Definition 18.18. E0CNT: USB0 Endpoint0 Data Count
USB Register Address = 0x16
18.11. Configuring Endpoints1-2
Endpoints1-2 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (USB Register Definition 18.4).
Endpoints1-2 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 18.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = 1, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = 0, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.
Endpoints1-2 can be disabled individually by the corresponding bits in the ENABLE register. When an End-
point is disabled, it will not respond to bus traffic or stall the bus. All Endpoints are enabled by default.
140
Name
Reset
6:0 E0CNT[6:0] Endpoint 0 Data Count.
Bit
Type
7
Bit
Unused
Name
R
7
0
Unused. Read = 0b. Write = don’t care.
This 7-bit number indicates the number of received data bytes in the Endpoint 0
FIFO. This number is only valid while bit OPRDY is a 1.
6
0
5
0
Rev. 1.1
4
0
E0CNT[6:0]
Function
R
3
0
2
0
1
0
0
0
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