C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 49
C8051T622-GMR
Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet
1.C8051T622-GMR.pdf
(254 pages)
Specifications of C8051T622-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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9. Prefetch Engine
The C8051T622/3 and C8051T326/7 family of devices incorporate a 2-byte prefetch engine. Because the
access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the
prefetch engine is necessary for full-speed code execution. Instructions are read from EPROM memory
two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute. When run-
ning linear code (code without any jumps or branches), the prefetch engine allows instructions to be exe-
cuted at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles
while the next set of code bytes is retrieved from EPROM memory.
Note: The prefetch engine should be disabled when the device is in suspend mode to save power.
SFR Definition 9.1. PFE0CN: Prefetch Engine Control
SFR Address = 0xAF
Name
Reset
Bit
7:6
4:0
Type
5
Bit
Unused
Unused
Name
PFEN
R
7
0
Unused. Read = 00b, Write = don’t care.
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Unused. Read = 00000b. Write = don’t care.
R
6
0
PFEN
R/W
5
1
C8051T622/3 and C8051T326/7
Rev. 1.1
R
4
0
Function
R
3
0
R
2
0
R
1
0
R
0
0
49
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