C8051T622-GMR Silicon Labs, C8051T622-GMR Datasheet - Page 27
C8051T622-GMR
Manufacturer Part Number
C8051T622-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN24
Manufacturer
Silicon Labs
Datasheet
1.C8051T622-GMR.pdf
(254 pages)
Specifications of C8051T622-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
Available stocks
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Price
Company:
Part Number:
C8051T622-GMR
Manufacturer:
SILICON
Quantity:
5 000
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Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.90 mm openings on a 1.1mm pitch should be used for the center pad to
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
C1
C2
X1
E
mask and the metal pad is to be 60 m minimum, all the way around the pad.
to assure good solder paste release.
assure the proper paste volume (67% Paste Coverage).
Body Components.
Figure 5.2. QFN-28 Recommended PCB Land Pattern
Table 5.2. QFN-28 PCB Land Pattern Dimensions
0.20
Min
4.80
4.80
0.50
C8051T622/3 and C8051T326/7
Max
0.30
Rev. 1.1
Dimension
X2
Y1
Y2
3.20
0.85
3.20
Min
3.30
Max
3.30
0.95
27
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