EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 60

• Manufacturer Part Number: EMC326SP16AK
• Description: 2mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Figure 49. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
Note:
1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from
clocks); WAIT active LOW; WAIT asserted during delay.
fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every t
A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
LB#/UB#
DQ[15:0]
A[20:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
High-Z
High-Z
READ Burst Identified
Valid Address
t
t
SP
CSP
(WE# = HIGH)
t
t
SP
t
t
CEW
SP
SP
t
t
t
HD
HD
HD
t
OLZ
t
BOE
t
t
ACLK
KHTL
t
CLK
Valid Output
60
t
KOH
t
HD
t
t
OHZ
HZ
t
CBPH
Note 2
High-Z
t
CEW
t
AS
EMC326SP16AK
Don’t Care
t
Valid Address
CW
t
BW
2Mx16 CellularRAM
t
AW
t
t
WC
WP
Valid Input
t
DW
t
HZ
t
t
WR
DH
t
Undefined
WPH
CEM
.