EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 22

• Manufacturer Part Number: EMC326SP16AK
• Description: 2mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

All must be set to “0” Must be set to “0”
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit
contained in the RCR. Figure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE
HIGH and A[19:18] = 10b, or through the register access software sequence with DQ = 0001h on the third cycle.
Figure 16: Bus Configuration Register Definition
Note: 1. Burst wrap and length apply to both READ and WRITE operations.
Reserved
BCR[19] BCR[18] Register Select
A[20]
20
0
1
0
A[19:18] A[17:16]
BCR[15]
Register
Select
19-18
0
1
0
0
1
Reserved
BCR[14]
BCR[13] BCR[12] BCR[11]
Synchronous burst access mode
Asynchronous access mode (default)
Select RCR
Select BCR
Select DIDR
17-16
0
1
0
0
0
0
1
1
1
1
Operating
Variable (default)
Fixed
Operating Mode
Mode
Initial Access Latency
A15
15
0
0
1
1
0
0
1
1
Latency
Initial
A14 A13 A12 A11
14
0
1
0
1
0
1
0
1
13
BCR[10]
Code 8
Code 1 - Reserved
Code 2
Code 3 (default)
Code 4
Code 5
Code 6
Code 7 - Reserved
Latency
Counter
12
0
1
Latency Counter
11
Active LOW
Active HIGH (default)
Polarity
WAIT
A10
10
Must be set to “0”
WAIT Polarity
Reserved
A9
9
22
Configuration(WC)
WAIT
A8
8
Must be set to “0”
BCR[3]
BCR[5] BCR[4] Drive Strength
BCR[8]
BCR[2] BCR[1] BCR[0] Burst Length (Note 1)
Reserved Reserved
0
1
0
0
1
1
0
1
0
0
0
1
1
A7
7
Must be set to “0”
Others
Burst wraps within the burst length
Burst no wrap (default)
Asserted during delay
Asserted one data before delay(default)
0
1
0
1
0
1
1
0
1
A6
6
Burst Wrap (Note 1)
WAIT Configuration
EMC326SP16AK
Full
1/2 (default)
1/4
Reserved
Strength
A5 A4
1
0
1
0
1
5
Drive
2Mx16 CellularRAM
4
4 words
8 words
16 words
32 words
Continuous burst (default)
Reserved
Wrap(BW)*
Burst
A3
3
Length(BL)*
A2 A1 A0
2
Burst
1
0