EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 25

• Manufacturer Part Number: EMC326SP16AK
• Description: 2mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data
value transferred. For allowable latency codes, see Tables 5 and 6, respectively, and Figures 18 and 19, respectively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to
detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that
allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It
is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency
counter. (See Table 6 and Figure 19)
Table 5: Variable Latency Configuration Codes
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
Figure18: Latency Counter (Variable Initial Latency, No Refresh Collision)
BCR[13:11]
DQ[15:0]
DQ[15:0]
Others
A[20:0]
010
100
011
ADV#
CLK
V
V
V
V
V
V
V
V
V
V
OH
OH
IH
IH
IH
OL
OL
IL
IL
IL
2 (3 clocks)
3 (4 clocks)-default
4 (5 clocks)
Reserved
Configuration
Address
Valid
Latency
Code
Code 3
Code 2
(default)
Normal
2
3
4
-
Latency
Output
Valid
Refresh Collision
25
1
6
8
4
-
Output
Output
Valid
Valid
104(9.62ns) 104(9.62ns)
133(7.5ns)
66(15ns)
Output
Output
Max Input CLK Frequency (MHz)
Valid
Valid
133
-
EMC326SP16AK
Don’t Care
66(15ns)
2Mx16 CellularRAM
Output
Output
Valid
Valid
104
-
-
52(19.2ns)
80(12.5ns)
Undefined
Output
Output
Valid
Valid
80
-
-