EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 4

• Manufacturer Part Number: EMC326SP16AK
• Description: 2mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

List of Figures
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Figure 10: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ............................ 17
Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation .............................. 18
Figure 12: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation .................................................... 19
Figure 13: Register READ, Synchronous Mode, Followed by READ ARRAY Operation ...................................................... 20
Figure 14: Load Configuration Register ................................................................................................................................ 21
Figure 15: Read Configuration Register ............................................................................................................................... 21
Figure 16: Bus Configuration Register Definition .................................................................................................................. 22
Figure 17: WAIT Configuration During Burst Operation ........................................................................................................ 24
Figure 18: Latency Counter (Variable Initial Latency, No Refresh Collision) ......................................................................... 25
Figure 19: Latency Counter (Fixed Latency) ........................................................................................................................ 26
Figure 20: Refresh Configuration Register Mapping ............................................................................................................. 27
Figure 21: AC Input/Output Reference Waveform ................................................................................................................ 30
Figure 22: AC Output Load Circuit ........................................................................................................................................ 30
Figure 23: Initialization Period .............................................................................................................................................. 35
Figure 24: DPD Entry and Exit Timing Parameters ............................................................................................................... 35
Figure 25: Asynchronous READ ........................................................................................................................................... 36
Figure 26: Asynchronous READ Using ADV# ....................................................................................................................... 37
Figure 27: PAGE MODE READ ........................................................................................................................................... 38
Figure 28: Single-Access Burst READ Operation - Variable Latency ................................................................................... 39
Figure 29: 4-Word Burst READ Operation - Variable Latency .............................................................................................. 40
Figure 30: Single-Access Burst READ Operation - Fixed Latency ........................................................................................ 41
Figure 31: 4-Word Burst READ Operation - Fixed Latency ................................................................................................... 42
Figure 32: READ Burst Suspend .......................................................................................................................................... 43
Figure 33: Burst READ at End-of-Row (Wrap off) ................................................................................................
Figure 34: Burst READ Row Boundary Crossing .................................................................................................................. 45
Figure 35: CE# - Controlled Asychronous WRITE ................................................................................................................ 46
Figure 36: LB#/UB# - Controlled Asychronous WRITE ......................................................................................................... 47
Figure 37: WE# - Controlled Asychronous WRITE ............................................................................................................... 48
Figure 38: Asynchronous WRITE Using ADV# ..................................................................................................................... 49
Figure 39: Burst WRITE Operation - Variable Latency Mode ............................................................................................... 50
Figure 40: Burst WRITE Operation - Fixed Latency Mode .................................................................................................... 51
Figure 41: Burst WRITE at End-of-Row (Wrap off) ............................................................................................................... 52
Figure 42: Burst WRITE Row Boundary Crossing ................................................................................................................ 53
Figure 43: Burst WRITE Followed by Burst READ ................................................................................................................ 54
Figure 44: Burst READ Interrupted by Burst READ or WRITE .............................................................................................. 55
Figure 45: Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode .................................................... 56
Figure 46: Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode ......................................................... 57
Figure 47: Asynchronous WRITE Followed by Burst READ ................................................................................................. 58
Figure 48: Asynchronous WRITE (ADV# LOW) Followed by Burst READ ........................................................................... 59
Figure 49: Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ................................................................... 60
Figure 50: Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................. 61
Figure 51: Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ............................................................. 62
Figure 52: Asynchronous WRITE Followed by Asynchronous READ ................................................................................... 63
Functional Block Diagram - 2 meg x 16 ............................................................................................................... 6
Power-Up Initialization Timing ............................................................................................................................. 9
READ Operation (ADV# LOW) ............................................................................................................................ 10
WRITE Operation (ADV# LOW) ........................................................................................................................... 11
Page Mode READ Operation (ADV# LOW) ......................................................................................................... 11
Burst Mode READ (4-word burst)......................................................................................................................... 12
Burst Mode WRITE (4-word burst)........................................................................................................................ 13
Refresh Collision During Variable-Latency READ Operation ............................................................................... 14
Wired or WAIT Configuration .............................................................................................................................
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EMC326SP16AK
2Mx16 CellularRAM
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