EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 59
EMC326SP16AK
Manufacturer Part Number
EMC326SP16AK
Description
2mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
1.EMC326SP16AK.pdf
(64 pages)
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Figure 48. Asynchronous WRITE (ADV# LOW) Followed By Burst READ
Note:
1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: Fixed or variable latency; latency code two (three
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to
clocks); WAIT active LOW; WAIT asserted during delay.
fixed-latency burst READs. A refresh opportunity must be provided every t
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
LB#/UB#
DQ[15:0]
IN/OUT
A[20:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
High-Z
Valid Address
t
CW
t
WC
t
WP
Data
t
DH
t
WPH
t
WC
Valid Address
t
t
AW
BW
t
t
DW
Data
WC
t
WR
59
Note 2
t
CBPH
CEM
. A refresh opportunity is satisfied by either of the following two
Valid Address
t
t
t
t
CSP
SP
SP
CEW
t
V
t
V
SP
SP
OH
OL
t
HD
t
t
HD
t
HD
CLK
High-Z
t
t
BOE
ACLK
EMC326SP16AK
Output
Don’t Care
Valid
t
KOH
2Mx16 CellularRAM
Output
Valid
Output
Valid
Output
Valid
Undefined
t
HD
t
OHZ
High-Z
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