M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 78
M1AFS250-FGG256I
Manufacturer Part Number
M1AFS250-FGG256I
Description
Actel Fusion Family Of Mixed Signal Fpgas
Manufacturer
Actel Corporation
Datasheet
1.M1AFS250-FGG256.pdf
(330 pages)
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Device Architecture
2- 62
DINA and DINB
These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all
configurations. When a data width less than nine is specified, unused high-order signals must be
grounded
DOUTA and DOUTB
These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA
and DINB, high-order bits may not be used
Table 2-29 • Unused/Used Input and Output Data Pins for Various Supported Bus Widths
D×W
4k×1
2k×2
1k×4
512×9
Note:
The "x" in DINx and DOUTx implies A or B.
(Table
2-29).
Unused
None
[8:1]
[8:2]
[8:4]
(Table
R e visio n 1
2-29). The output data on unused pins is undefined.
DINx/DOUTx
Used
[1:0]
[3:0]
[8:0]
[0]
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