M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 326

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Datasheet Information
5- 10
Revision
Advance v0.6
(October 2006)
The second paragraph of the
information about POWERDOWN.
The description for bit 0 was updated in
3.9 was changed to 7.8 in the
All function descriptions in
In
updated.
The
The
Table 2-35 • FIFO
The VAREF function description was updated in
Description.
The
mode and sleep mode.
The text in the
The
the drain.
The
statement:
"All results are MSB justified in the ADC."
The information about the ADCSTART signal was updated in the
section.
Table 2-46 · Analog Channel Specifications
Table 2-47 · ADC Characteristics in Direct Input Mode
Table 2-51 • ACM Address Decode Table for Analog Quad
In
Setting for Bit 6 in Byte 3 was updated.
The
outputs, and bibufs.
In
updated for the following features:
Single-ended receiver
Voltage-referenced differential receiver
LVDS/LVPECL differential receiver features
The
descriptions
The
information about avoiding high current draw.
The
include information about avoiding high current draw.
The
statement: VMV and V
pins within a given I/O bank.
Table 2-69 • Fusion Pro I/O
Table 2-19 • Flash Memory Block Pin
Table 2-53 • Analog Quad ACM Byte
"RESET" section
"RESET" section
"Voltage Monitor" section
"Gate Driver" section
"Introduction" section
"V
"User I/O Naming Convention" section
"Analog-to-Digital Converter Block" section
"V
"VMVx I/O Supply Voltage (quiet)" section
CCNVM
CC33PMP
Flash Memory Block Power Supply (1.5 V)" section
"Current Monitor" section
Analog Power Supply (3.3 V)" section
was updated.
was updated.
was updated.
CCI
Table 2-18 · Signals for VRPSM
was updated to include information about forcing 1 V on
must be connected to the same power supply and V
was updated to include information about digital inputs,
"Crystal Oscillator (Xtal Osc)"
was updated to include information about low power
Features, the programmable delay descriptions were
"PLL Macro" section
R e visio n 1
Changes
Table 2-17 · RTC Control/Status
was changed from 2 mV to 1 mV.
was updated.
Assignment, the Function and Default
Names, the RD[31:0] description was
was updated to include "V" and "z"
was updated with the following
Table 2-36 • Analog Block Pin
was updated to include this
was updated.
was updated to include
was updated to include
Macro.
section.
was updated.
"ADC Description"
was updated to
Register.
CCI
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2-137
2-159
2-224
2-224
2-185
Page
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