M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 240

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Device Architecture
Figure 2-143 • Output DDR Timing Diagram
Table 2-179 • Output DDR Propagation Delays
2- 22 4
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_F
Data_R
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
CLK
CLR
Out
DDOMAX
For the derating values at specific junction temperature and voltage supply levels, refer to
page
6
Commercial Temperature Range Conditions: T
3-9.
t
DDROCLR2Q
1
Timing Characteristics
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROSUD1
7
2
t
t
DDROCLKQ
DDROHD1
7
Description
t
DDROSUD2
8
3
2
R e visio n 1
t
DDROHD2
J
= 70°C, Worst-Case VCC = 1.425 V
8
4
9
3
1,048
t
0.70
0.38
0.38
0.00
0.80
0.00
0.22
0.22
0.36
0.32
0.00
DDRORECCLR
–2
9
1,232
0.80
0.43
0.43
0.00
0.00
0.91
0.00
0.25
0.25
0.41
0.37
10
4
–1
5
1,404
0.94
0.51
0.51
0.00
0.00
1.07
0.00
0.30
0.30
0.48
0.43
Std.
Table 3-7 on
10
Units
11
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns