M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 49
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M1AFS250-FGG256I
Manufacturer Part Number
M1AFS250-FGG256I
Description
Actel Fusion Family Of Mixed Signal Fpgas
Manufacturer
Actel Corporation
Datasheet
1.M1AFS250-FGG256.pdf
(330 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M1AFS250-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Real-Time Counter System
Note:
Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro)
XTLOSC
MODE[1:0]
FPGA_EN*
Real-Time Counter
AB
*Signals are hardwired internally and do not exist in the macro core.
Crystal Clock
RTCXTLSEL
XTAL1
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce
power consumption in many applications.
The RTC system is composed of five cores:
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during
standby mode.
SELMODE
•
•
•
•
•
•
•
XTL*
XTL
Sleep mode, typical 10 µA
Standby mode (RTC running), typical 3 mA with 20 MHz
RTC sub-block inside Analog Block (AB)
Voltage Regulator and Power System Monitor (VRPSM)
Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock
Resources chapter of the
Crystal clock; does not require instantiation in RTL
1.5 V voltage regulator; does not require instantiation in RTL
XTAL2
RTCXTLMODE[1:0]
RTC_MODE[1:0]
RTCPSMMATCH
RTCMATCH
Figure 2-27
RTCCLK
CLKOUT
shows their connection.
Can Be Route
to PLL
Fusion FPGA Fabric User’s Guide
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
PUB
R e v i s i o n 1
Power-Up/-Down
Toggle Control
Switch
TRST*
FPGAGOOD
PUCORE
VREN*
Actel Fusion Family of Mixed Signal FPGAs
1.5 Voltage Regulator
VREN*
for more detail.
External Pin
Internal Pin
Cores do not require any
RTL instantiation
Cores require RTL instantiation
Sub-block in cores does not
require additional RTL instantiation
PTBASE*
PTEM*
3.3 V
External
Pass
Transistor
2N2222
1.5 V
2- 33
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