M1AFS250-FGG256I Actel Corporation, M1AFS250-FGG256I Datasheet - Page 31

• Manufacturer Part Number: M1AFS250-FGG256I
• Description: Actel Fusion Family Of Mixed Signal Fpgas
• Manufacturer: Actel Corporation

Clock Aggregation
Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to
allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock
aggregation system is achieved through long-line resources in the central rib, and also through local
resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As
indicates, this access system is contiguous.
There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from
the quadrant clocks, located in these ribs, which only reach the middle of the rib.Refer to the
Global Resources in Actel Fusion Devices
Figure 2-14 • Clock Aggregation Tree Architecture
Tree Node MUX
Global Driver and MUX
Global Spine
Global Rib
application note.
R e v i s i o n 1
I/O Access
Internal Signal Access
Global Signal Access
Actel Fusion Family of Mixed Signal FPGAs
I/O Tiles
Figure 2-14
Using
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