STAC9766 IDT [Integrated Device Technology], STAC9766 Datasheet - Page 81

• Manufacturer Part Number: STAC9766
• Manufacturer: IDT [Integrated Device Technology]

9. LOW POWER MODES
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
The STAC9766/9767 is capable of operating at reduced power when no activity is required. The
power-down state is controlled by the Powerdown Register (26h). There are seven separate
power-down commands. The power down options are listed in Table 29. The first three bits,
PR0..PR2, can be used individually or in combination with each other, and control power distribution
to the ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and refer-
ence voltages, and can only be used in combination with PR1, PR2 and PR3. PR3 essentially
removes power from all analog sections of the CODEC and is generally only asserted when the
CODEC will not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only.
PR2 and PR3 do not need to be “set” before a PR4, but PR0 and PR1 should be “set” before PR4.
PR5 disables the DSP clock and does not require an external cold reset for recovery. PR6 disables
the headphone driver amplifier for additional analog power saving.
Figure 22 illustrates an example procedure to do a complete power down of STAC9766/9767. From
normal operation, sequential writes to the Powerdown Register are performed to power down
STAC9766/9767 a section at a time. After everything has been shut off, a final write (of PR4) can be
executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding
their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,
issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9766/9767 can
also be woken up with a cold reset. A cold reset will reset all of the registers to their default states
(Paged Registers are semi-exempt). When a section is powered back on, the Powerdown Control/
Status register (index 26h) should be read to verify that the section is ready (stable) before attempt-
ing any operation that requires it.
N o r m a l
Figure 22. Example of STAC9766/9767 Powerdown/Powerup Flow
P R 0 = 0 & A D C = 1
P R 0 = 1
GRP Bits
PR0
PR1
PR2
PR3
PR4
PR5
PR6
Ready =1
A D C s o f f P R 0
P R 1 = 0 & D A C = 1
P R 1 = 1
D A C s o f f P R 1
PCM in ADCs & Input Mux Powerdown
PCM out DACs Powerdown
Analog Mixer power down (VREF still on)
Analog Mixer power down (VREF off)
Digital Interface (AC-Link) power down (BIT_CLK forced low)
Digital Clock disable, BIT_CLK still on
Powerdown HEADPHONE_OUT
Default
Table 29. Low Power Modes
P R 2 = 0 & A N L = 1
81
P R 2 = 1
P R 2 o r P R 3
Analog off
Cold Reset
P R 4 = 1
Function
Digital I/F off
W a r m R e s e t
STAC9766/9767
P R 4
Shut off
AC-Link
PC AUDIO
V 7.4 12/06