STAC9766 IDT [Integrated Device Technology], STAC9766 Datasheet - Page 31

• Manufacturer Part Number: STAC9766
• Manufacturer: IDT [Integrated Device Technology]

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
5.3.
AC-link Output Frame (SDATA_OUT)
The AC-link output frame data streams correspond to the multiplexed bundles of all digital output
data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-link output
frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot
containing 16-bits which are used for AC-link protocol infrastructure.
Figure 15 illustrates the time slot based AC-link protocol.
A new AC-link output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-
troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-
tion is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97
CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0 by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid
time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0.
As an example, consider an 8-bit sample stream that is being played out to one of the STAC9766/
9767 DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next
SDATA_OUT
BIT_CLK
End of previous audio frame
SYNC
S D A T A _ O U T
B I T _ C L K
E n d o f p r e v i o u s a u d i o f r a m e
12.288 MHz
Figure 16. Start of an Audio Output Frame
Frame
Figure 15. AC-Link Audio Output Frame
valid
S Y N C
slot1 slot2
Tag Phase
("1" = time slot contains valid PCM data)
a s s e r t e d
S Y N C
Time Slot "Valid" Bits
slot(12)
"0"
31
d e t e c t e d b y
S Y N C
c o d e c
CID1
F r a m e
v a l i d
CID0
19
s l o t 1
S D A T A _ O U T
Slot 1
b i t o f f r a m e
f i r s t
"0"
s l o t 2
19
STAC9766/9767
Slot 2
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
PC AUDIO
19
V 7.4 12/06
Slot 12
"0"