STAC9766 IDT [Integrated Device Technology], STAC9766 Datasheet - Page 34

• Manufacturer Part Number: STAC9766
• Manufacturer: IDT [Integrated Device Technology]

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
5.4.
5.3.6.
5.3.7.
5.3.8.
AC-link Input Frame (SDATA_IN)
olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-
tions within this time slot with 0.
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 5: Not Used by STAC9766/9767 (Modem Line 1 Output Channel)
Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9766/9767
Slot 6 -11: DAC
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 12: Audio GPIO Control Channel
AC-link output frame slot 12 contains the audio GPIO control outputs.
The AC-link input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC‘97 Controller. As is the case for audio output frame, each AC-link input frame con-
sists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are
used for AC-link protocol infrastructure.
The following diagram illustrates the time slot-based AC-link protocol.
A new AC-link input frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97 CODEC
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are
aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 CODEC transi-
tions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit position is pre-
sented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97 Controller
on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subse-
quent sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN
BIT_CLK
End of previous audio frame
SYNC
12.288 MHz
Figure 17. STAC9766/9767 Audio Input Frame
Frame
valid
slot1
Tag Phase
slot2
("1" = time slot contains valid PCM data)
Time Slot "Valid" Bits
slot(12)
"0"
34
"0"
"0"
19
Slot 1
"0"
19
STAC9766/9767
Slot 2
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
PC AUDIO
19
Slot 12
V 7.4 12/06
"0"
.