STAC9766 IDT [Integrated Device Technology], STAC9766 Datasheet - Page 24

• Manufacturer Part Number: STAC9766
• Manufacturer: IDT [Integrated Device Technology]

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
4.5.
4.4.2.
AC-link Power Management
4.5.1.
4.5.2.
STAC9766/9767 as a Secondary CODEC
Secondary devices are required to function correctly using one or more of the following clocking
options:
•
•
Powering down the AC-link
The AC-link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h)
is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a
logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to
play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.
BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Pow-
erdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to
program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream
in the audio output frame.
After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required
to drive and keep SYNC and SDATA_OUT low.
Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be
used to bring the AC-link to the active mode, since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
Waking up the AC-link
There are two methods for bringing the AC-link out of a low power, halted mode. Regardless of the
method, it is the AC‘97 Controller that performs the wake-up task.
See section 2.2.3: page14 for clock frequencies supported and configurations.
S D A T A _ O U T
24.576 MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary
24.576 MHz clock)
BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored.
S D A T A _ I N
B I T _ C L K
N o t e : B I T _ C L K n o t t o s c a l e
S Y N C
Figure 13. STAC9766/9767 Powerdown Timing
f r a m e
f r a m e
s l o t 2
s l o t 2
p e r
p e r
24
T A G
T A G
W r i t e t o
0 x 2 0
D A T A
P R 4
STAC9766/9767
PC AUDIO
V 7.4 12/06