STAC9766 IDT [Integrated Device Technology], STAC9766 Datasheet
STAC9766
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STAC9766 Summary of contents
Page 1
... Supported audio sample rates include 48KHz, 44.1KHz, 32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8 KHz; addi- tional rates are supported in the STAC9766/9767 soft audio drivers. All ADCs and DACs operate at 20-bit resolu- tion. The STAC9766/9767 includes full Stereo Microphone ...
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... LOW POWER MODES ...........................................................................................................81 10. MULTIPLE CODEC SUPPORT ............................................................................................83 10.1. Primary/Secondary CODEC Selection .......................................................................................... 83 10.2. Secondary CODEC Register Access Definitions .......................................................................... 84 11. TESTABILITY ........................................................................................................................85 11.1. ATE Test Mode ............................................................................................................................. 85 12. ORDERING INFORMATION ..................................................................................................86 12.1. STAC9766/9767 Family Options and Part Order Numbers ...........................................................86 13. PIN DESCRIPTION ................................................................................................................87 13.1. Digital I/O ...................................................................................................................................... 88 13.2. Filter/References .......................................................................................................................... 88 13.3. Analog I/O .................................................................................................................................... 89 13.4. Power and Ground Signals .......................................................................................................... 90 IDT™ ...
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... TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 14. PACKAGE DRAWING ...........................................................................................................91 14.1. 48-Pin LQFP .................................................................................................................................. 91 15. SOLDER REFLOW PROFILE ...............................................................................................92 15.1. Standard Reflow Profile Data ........................................................................................................ 92 15.2. Pb Free Process - Package Classification Reflow Temperatures ................................................. 93 16. APPENDIX A: PROGRAMMING REGISTERS .....................................................................94 17. REVISION HISTORY .............................................................................................................96 IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 3 STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... Figure 19. Bi-directional AC-link Frame with Slot assignments ....................................................................39 Figure 20. STAC9766 2-Channel Mixer Functional Diagram .......................................................................42 Figure 21. STAC9767 2-Channel Mixer Functional Diagram .......................................................................42 Figure 22. Example of STAC9766/9767 Powerdown/Powerup Flow ...........................................................81 Figure 23. Powerdown/Powerup Flow With Analog Still Alive .......................................................................82 Figure 24. Pin Description Drawing ............................................................................................................... 87 Figure 25. 48-Pin LQFP Package Outline and Package Dimensions ...........................................................91 Figure 26. Solder Reflow Profile ................................................................................................................... 92 IDT™ ...
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... Table 30. CODEC ID Selection .....................................................................................................................83 Table 31. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................84 Table 32. Test Mode Activation .....................................................................................................................85 Table 33. ATE Test Mode Operation ............................................................................................................. 85 Table 34. STAC9766/9767 Ordering Information .......................................................................................... 86 Table 35. Digital Connection Signals ............................................................................................................. 88 Table 36. Filtering and Voltage References .................................................................................................. 88 Table 37. Analog Connection Signals ........................................................................................................... 89 Table 38. Power and Ground Signals ............................................................................................................ 90 IDT™ ...
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... I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9766/9767 includes digital output capability for support of modern PC systems with an output that supports the SPDIF format. The STAC9766/9767 is a standard 2-channel stereo CODEC. With IDT’s headphone drive capability, headphones can be driven without an external amplifier ...
Page 7
... SoftEQ configurations. The fully parametric IDT SoftEQ can be initiated upon jack insertion and sensed impedance levels. The STAC9766/9767 also offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP is a new feature added to the AC’97 Specification Rev 2.3. ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING STAC9766/9767 provides for a stereo enhancement feature, IDT Surround 3D (SS3D). SS3D pro- vides the listener with several options for improved speaker separation beyond the normal 2- or 4-speaker arrangements. The STAC9766/9767 can be SoundBlaster with IDT’ ...
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... Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the STAC9766/9767. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (AC-Link outputs - Hi-Z) Output buffer drive current 2.1.5. STAC9766 Analog Performance Characteristics ( ºC, AVdd = 5.0 V ± 5%, DVdd = 3.3 V ± 5%, AVss = DVss = KHz input sine ambient wave; Sample Frequency = 48 KHz; 0dB = 1 Vrms BW – ...
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... Min Typ Max Unit - 20,000 - 19,200 19,200 - 28,800 28,800 - - 100 - - 100 - - 100 - - 1 0.5 x AVdd - - - 0 0.5 50 pFload, TestbenchCharacterization Min Typ Max Unit - 1.0 - Vrms - 0.03 - Vrms - 0.5 - Vrms STAC9766/9767 V 7.4 12/ ...
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... PC AUDIO Min Typ Max Unit 0.5 Vrms - 0.5 - Vrms - 12 20,000 19,200 Hz 19,200 - 28,800 Hz 28,800 - - Hz 100 - - 100 - dB - 100 - 0.5 X AVdd - 0 0 100 - ppm/ºC STAC9766/9767 V 7.4 12/06 ...
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... Figure 2. Cold Reset Timing Tres_low Parameter Figure 3. Warm Reset Timing Tsync_high Parameter 13 PC AUDIO Trst2clk Ttri2actv Ttri2actv Symbol Min Typ Max Tres_low 1.0 - Tri2actv - - 25 Trst2clk 0.01628 - 400 Tclk2rst 0.416 - Tsync_2clk Symbol Min Typ Max Tsync_high 1.0 1.3 - Tsync2clk 162 STAC9766/9767 Units - Units 7.4 12/06 ...
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... STAC9766/9767 Crystal Elimination Circuit and Clock Frequencies The STAC9766/9767 supports several clock frequency inputs as described in the following table. In general, when a 24.576 MHz xtal is not used, the XTALOUT pin should be tied to ground. This short to ground configures the part into an alternate clock mode and enables an on board PLL. ...
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... Figure 6. Signal Rise and Fall Times Timing Clock Frequency 24.576MHz 12.288MHz 14.31818MHz 27MHz 48MHz T setup Symbol Min Typ Max Tsetup 10 - Thold 10 - tco - - STAC9766/9767 PC AUDIO Units - 7.4 12/06 ...
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... SDATA_OUT high for the trailing edge of RESET# causes the STAC9766/9767 AC-Link outputs to go high-impedance, which is suitable for ATE in-circuit testing. Note: 2) Once the test mode has been entered, the STAC9766/9767 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. ...
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... TUNE TO LAYOUT 11 RESET# 45 CID0 46 CID1 47 EAPD 28 VREFOUT 27 VREF 1 µ SPDIF 44 GPIO1 43 GPIO0 MONO_OUT 39 HP_OUT_L 40 HP_COMM should be tied to HP_COMM ground at the headphone pin. 41 HP_OUT_R *Terminate ground plane as close to codec as possible Analog Digital Ground Ground STAC9766/9767 PC AUDIO external pul- V 7.4 12/06 ...
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... Split Independent Power Supply Operation In PC applications, one power supply input to the STAC9766/9767 may be derived from a supply regulator and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's CODECs would be subject to on-chip SCR type latch-up ...
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... AFILT2 IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Figure 10. Split Independent Power Supply Operation *Suggested 0.1 µF 0.1 µ AVdd1 AVdd2 DVdd1 STAC9766 (5V Analog) or STAC9767 (3.3V Analog) AVss1 AVss2 DVss1 DVss2 3.3V ± µF 0.1 µF ...
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... AC-link Physical interface The STAC9766/9767 communicates with its companion Digital Controller via the AC-link digital serial interface. AC-link has been defined to support connections between a single Controller and up to four CODECs. All digital audio, modem, and handset data streams, as well as all control (com- ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING The STAC9766/9767 uses the XTAL_OUT pin (pin 3) and the CID0 and CID1 pins (pins 45 & 46) to determine its alternate clock frequencies. See section 2.2.4: page14 for additional information on Crystal Elimination and for supported clock frequencies. ...
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... Secondary devices must be configurable (via hardwiring, strap pin(s), or other meth- ods) as CODEC IDs 01, 10 the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s). IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 22 STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... Using the Primary’s BIT_CLK output to derive 24.576 MHz See section 2.2.3: page14 for clock frequencies supported and configurations. 4.4.1. STAC9766/9767 as a Primary CODEC Primary devices are required to support correctly either of the following clocking options: • 24.576 MHz crystal attached to XTAL_IN and XTAL_OUT • ...
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... There are two methods for bringing the AC-link out of a low power, halted mode. Regardless of the method the AC‘97 Controller that performs the wake-up task. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Figure 13. STAC9766/9767 Powerdown Timing ...
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... When AC-link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit 15). 4.5.3. CODEC Triggers Wake-up The STAC9766/9767 (running off Vaux) can trigger a wake event (PME#) by transitioning SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the AC-link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID, etc. ...
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... AC‘97. This will preclude the false detection of a new audio frame. 4.5.4.3. Most registers device can be restored to their default values by performing a write (any value) to the Reset Register, 00h. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Register AC‘97 Reset 26 PC AUDIO STAC9766/9767 V 7.4 12/06 ...
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... PCM audio streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. The STAC9766/9767 DACs, ADCs and SPDIF can be assigned to slots 3&4, 6&9, 7&8 or 10&11. Figure 14. Bi-directional AC-link Frame with Slot Assignments OUTGOING STREAMS ...
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... MSBs echo register address; LSBs indicate which slots request data 20-bit PCM data from Left and Right inputs 16-bit modem data from modem Line1 input 20-bit PCM data - Alternative Slots for Input GPIO Status 28 Description 16-bit command register read data GPIO read port and interrupt status STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Table 6. VRA Behavior VRA = 0 always 0 (data each frame) forced to 48 KHz 29 STAC9766/9767 PC AUDIO VRA = (data on demand) writable V 7.4 12/06 ...
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... Secondary CODEC ID bits not valid. AC‘97 Digital Controllers should set the frame valid bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the Secondary CODEC ID bits are set. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 30 STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with example, consider an 8-bit sample stream that is being played out to one of the STAC9766/ 9767 DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next IDT™ ...
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... Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only) Slot 3-12 Valid Data bits Slot 3: PCM Left channel Slot 4: PCM Right channel Slot 5: Modem Line 1 (not used on STAC9766/9767) Slot 6: Alternative PCM1 Left Slot 7: Alternative PCM2 Left Slot 8: Alternative PCM2 Right Slot 9: Alternative PCM1 Right ...
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... Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless required to be readable as well as writeable to provide more robust testability. AC-link output frame slot 1 communicates control register address, and write/read command infor- mation to the STAC9766/9767. Bit 19 18:12 11:0 The first bit (MSB) sampled by AC‘ ...
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... The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.3.6. Slot 5: Not Used by STAC9766/9767 (Modem Line 1 Output Channel) Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9766/9767 5.3.7. Slot 6 -11: DAC The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. ...
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... Slot 1: Status Address Port / SLOTREQ signaling bits 5.4.2.1. The status port is used to monitor status for the STAC9766/9767 functions including, but not limited to, mixer settings and power management. AC-link input frame slot 1’s stream echoes the control 1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready the responsibility of the AC’97 controller to probe more deeply into the AC‘ ...
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... Echo of register index for which data is being returned SLOTREQ See Next Section Reserved Stuffed with 0 SLOTREQ signaling bits Table 10. Status Data Port Bit Assignments Description Control Register Read Data Reserved 36 PC AUDIO Comments Comments Stuffed with 0 if tagged “invalid” Stuffed with 0 STAC9766/9767 V 7.4 12/06 ...
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... NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.8. Slots 7-8: Vendor Reserved The left and right ADC channels of the STAC9766/9767 may be assigned to slots 7&8 by Register 6Eh. NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. 5.4.9. Slot 10 & 11: ADC The left and right ADC channels of the STAC9766/9767 may be assigned to slots 10& ...
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... Table 12. Secondary CODEC Addressing: Slot 0 tag bits Slot 0, bit 15 Slot 0, bit 14 (Valid Frame) (Valid Slot 1 Address AUDIO Slot 0, bit 13 Slot 0, Bits 1-0 (Valid Slot 2 Data) (CODEC ID Slot 0, bit 13 Slot 0, Bits 1-0 (Valid Slot 2 Data) (CODEC ID) 0 01, 10 01, 10 STAC9766/9767 V 7.4 12/06 ...
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... Vendor Vendor Vendor ADC MIC RSVD RSVD RSVD ADC Slot 12 can be used by the AC'97 Codec if a Modem Codec is not present. Description Description STAC9766/9767 PC AUDIO SPDIF 7.4 12/06 ...
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... PCM data for left channel 20-bit PCM data for right channel 20-bit PCM data for Center channel 20-bit PCM data for L Surround channel 20-bit PCM data for R Surround channel 20-bit PCM data for LFE channel 20-bit SPDIF Output Reserved Description Description STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... STAC9766/9767 MIXER 6.1. Mixer Description The STAC9766/9767 includes an analog mixer for maximum flexibility. The analog mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. The analog mixer also includes several extensions of the AC’97 specification to support “ ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 6.2. Mixer Functional Diagrams Figure 20. STAC9766 2-Channel Mixer Functional Diagram 2Ah:D5-D4 Slot 6Ah:D1 Select 28h: D5-D4 Slot PCMOut Select DAC PC_BEEP Phone 20h:D8 0Eh:D6 & 6E:D2 MIC1 10 MIC2 Analog Audio LINEIN ...
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... TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 6.3. Mixer Analog Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9766/9767 supports the following input sources: • Any mono or stereo source • Mono or stereo mix of all sources • ...
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... PC Beep Implementation The STAC9766/9767 offers two styles of PC BEEP, Analog and Digital. The digital PC Beep is a new feature added to the AC’97 Specification Rev 2.3. This style of PC Beep will eventually replace the Analog style, thus eliminating the need for a PC Beep pin. Until this feature is widely accepted, IDT will provide BOTH styles of PC Beep ...
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... This will be programmed directly by the BIOS. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Table 18. Digital PC Beep Examples Value Reg 0Ah 1 0x01 10 0x0A 25 0x19 50 0x32 100 0x64 127 0x0F 255 0xFF 45 PC AUDIO Frequency 12,000Hz 1200Hz 480Hz 240Hz 120Hz 94.48Hz 47.05Hz STAC9766/9767 V 7.4 12/06 ...
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... PC AUDIO Location 8.1.1; page47 8.1.2; page48 8.1.3; page48 8.1.4; page49 8.1.5; page50 8.1.6; page50 8.1.7; page51 8.1.8; page51 8.1.9; page52 8.1.10; page53 8.1.11; page53 8.1.12; page54 8.1.13; page54 8.1.14; page55 8.1.15; page56 8.1.16; page56 8.1.17: page57 8.1.18; page58 8.1.19; page59 8.1.20; page60 8.1.22; page63 8.1.23; page63 8.1.24; page64 8.2.4; page66 8.2.5; page66 8.2.6; page66 8.2.7; page67 8.2.8; page67 8.2.9; page67 8.3; page68 8.4.2; page70 8.4.3; page70 8.4.4; page71 8.4.5; page72 8.4.6; page74 8.4.7: page74 8.4.7; page74 NA 8.4.9: page76 STAC9766/9767 V 7.4 12/06 ...
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... ID2 Bass & treble control ID1 Reserved ID0 Dedicated MIC PCM in channel 47 Default Location 0000h NA 0000h NA 0000h 8.4.10; page77 0800h 8.4.11; page78 0000h 8.4.12; page79 NA NA 8384h 8.5.1; page80 7652h 8.5.2; page80 D11 D10 D9 SE1 SE0 ID9 ID3 ID2 ID1 Description STAC9766/9767 PC AUDIO D8 ID8 D0 ID0 V 7.4 12/06 ...
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... Headphone attenuation is a function of bits12-8 ML5 1 = forces register bits 12 11111 Always reads back 0 48 D11 D10 D9 ML3 ML2 ML1 MR3 MR2 MR1 Description D11 D10 D9 HPL3 HPL2 HPL1 HPR3 HPR2 HPR1 Description STAC9766/9767 PC AUDIO D8 ML0 D0 MR0 D8 HPL0 D0 HPR0 V 7.4 12/06 ...
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... Bit not used, should read back Mono attenuation is a function of bits 4-0 MM5 1 = Forces register bits 4 11111 Always reads back 0 Mono Volume Control 00000 = 0dB attenuation MM<4:0> 00001 = 1.5dB attenuation ..... 11111 = 46.5dB attenuation 49 Description D11 D10 D9 RESERVED MM3 MM2 MM1 Description STAC9766/9767 PC AUDIO D8 D0 MM0 V 7.4 12/06 ...
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... Bit not used, should read back 0 Phone Volume Control 00000 = 12dB gain 00001 = 10.5dB gain GN<4:0> ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain 50 D11 D10 PV2 PV1 PV0 Description D11 D10 D9 RESERVED GN3 GN2 GN1 Description STAC9766/9767 PC AUDIO RSRVD D8 D0 GN0 V 7.4 12/06 ...
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... GL<4:0> ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain 51 D11 D10 D9 RESERVED GN3 GN2 GN1 Description = Mic Gain Boost D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description STAC9766/9767 PC AUDIO D8 D0 GN0 D8 GR0 D0 GR0 V 7.4 12/06 ...
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... RESERVED Bit not used, should read back 0 right CD Volume Control 00000 = 12dB gain 00001 = 10.5dB gain GR<4:0> ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain 52 Description D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description STAC9766/9767 PC AUDIO D8 GR0 D0 GR0 V 7.4 12/06 ...
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... Left Aux Volume Control 00000 = 12dB gain 00001 = 10.5dB gain GL<4:0> ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain 53 D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description STAC9766/9767 PC AUDIO D8 GR0 D0 GR0 D8 GR0 D0 GR0 V 7.4 12/06 ...
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... GR<4:0> ..... 01000 = 0dB gain ..... 11111 = -34.5dB gain D13 D12 RESERVED RESERVED 54 Description D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description D11 D10 D9 SL2 SL1 SR2 SR1 STAC9766/9767 PC AUDIO D8 GR0 D0 GR0 D8 SL0 D0 SR0 V 7.4 12/06 ...
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... RESERVED Bits not used, should read back 0 Right Channel Volume Control 0000 = 0dB gain GR<3:0> 0001 = 1.5dB gain .... 1111 = 22.5dB gain 55 Description D11 D10 D9 GL3 GL2 GL1 GR3 GR2 GR1 Description STAC9766/9767 PC AUDIO D8 GL0 D0 GR0 V 7.4 12/06 ...
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... LINE_OUT SEPARATION RATIO DP3 DP2 effect 0 0 DP3,DP2 4.5 ( MED ) 1 1 RESERVED Bits not used, should read back 0 56 D11 D10 D9 RESERVED MIX RESERVED Description D11 D10 DP3 DP2 RESERVED Description 0 ( OFF ) 3 ( LOW ) 6 ( HIGH ) STAC9766/9767 PC AUDIO 7.4 12/06 ...
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... CODEC interrupt infrastructure. In either case, software should poll the interrupt status after initiating a sense cycle and wait for Sense Cycle Max Delay to determine if an interrupting event has occurred. 57 D11 D10 D9 I0 RESERVED PG3 PG2 PG1 Description STAC9766/9767 PC AUDIO D8 D0 PG0 V 7.4 12/06 ...
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... ADC powered down RESERVED Bit not used, should read back 0 Read Only --- VREF status REF 1 = VREF enabled Read Only ---- ANALOG MIXERS, etc. Status ANL 1 = Analog mixers ready. 58 Description D11 D10 D9 PR3 PR2 PR1 REF ANL DAC Description STAC9766/9767 PC AUDIO D8 PR0 D0 ADC V 7.4 12/06 ...
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... When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. 8.1.18.2. The STAC9766/9767 is capable of operating at reduced power when no activity is required. The power-down state is controlled by the Powerdown Register (26h). See the section “Low Power Modes” for more information. ...
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... Reserved 0 = SPDIF pulled high on reset, SPDIF disabled 1 = default, SPDIF enabled (Note 2) Reserved Variable sample rates supported (Always = 1) external pulldown. To Disable SPDIF, use a D11 D10 D9 SPCV RESERVED RSRVD SPDIF RSRVD STAC9766/9767 PC AUDIO D8 D0 VRA enable V 7.4 12/06 ...
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... Bit not used, should read back VRA disabled, DAC and ADC set to 48 KHz (Registers 2Ch and 32h VRA Enable loaded with the value BB80h VRA ENABLED, Reg. 2Ch & 32h control sample rate Variable Rate Sampling Enable 61 PC AUDIO external pulldown. Description STAC9766/9767 V 7.4 12/06 ...
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... PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz). 8.1.20.2. The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the SPDIF functionality within the STAC9766/9767. If the SPDIF is set then the function is enabled. When set disabled. 8.1.20.3. ...
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... SR4 D13 D12 SR13 SR12 SR5 SR4 63 SR15-SR0 Value 1F40h 2B11h 3E80h 5622h 7D00h AC44h BB80h D11 D10 D9 SR11 SR10 SR9 SR3 SR2 SR1 D11 D10 D9 SR11 SR10 SR9 SR3 SR2 SR1 STAC9766/9767 PC AUDIO D8 SR8 D0 SR0 D8 SR8 D0 SR0 V 7.4 12/06 ...
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... Read & Write COPY 1 = Copyright is asserted 0 = PCM data Read & Write /AUDIO 1 = Non-Audio or non-PCM format 0 = Consumer use of the channel Read & Write PRO 1 = Professional use of the channel 64 D11 D10 D9 L CC6 CC5 PRE COPY /AUDIO Description (note 1-2) STAC9766/9767 PC AUDIO D8 CC4 D0 PRO V 7.4 12/06 ...
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... The GPIOs are set to a high impedance state on power- cold reset the AC‘97 Digi- tal Controller to first enable the output after setting it to the desired state. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 65 STAC9766/9767 PC AUDIO V 7.4 12/06 ...
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... GC1 (GPIO1) Description Bit not used, should read back GPIO1 configured as output 1 = GPIO1 configured as input 0 = GPIO0 configured as output 1 = GPIO0 configured as input D11 D10 GP1 (GPIO1) Description STAC9766/9767 PC AUDIO D8 PRA D0 GPIO D8 D0 GC0 (GPIO0 GP0 (GPIO0) V 7.4 12/06 ...
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... Value 0 RESERVED Bit not used, should read back 0 67 D11 D10 GS1 (GPIO1) GS0 (GPIO0) Description D11 D10 GW1 (GPIO1) GW0 (GPIO0) Description D11 D10 GI1 (GPIO1) Description STAC9766/9767 PC AUDIO GI0 (GPIO0) V 7.4 12/06 ...
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... GI0 When GPIO0 is configured as input and configured as a sticky, writing a 1 does nothing, writing a 0 clears this bit. When GPIO0 is configured as input, this register reflects the value on the GPIO0 pad after interpretation of the polarity and sticky configurations AUDIO Description STAC9766/9767 V 7.4 12/06 ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 8.4. STAC9766/9767 Paging Registers The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of regis- ters. The registers currently used in the paging are 60h to 6Eh. Additional information about the Extended CODEC Registers, please refer to Section 8.3: page68. ...
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... If data is not available, returns FFFFh. ) Page 01h D13 D12 PI13 PI12 PI6 PI5 PI4 70 Description D11 D10 D9 PVI11 PVI10 PVI9 PVI3 PVI2 PVI1 Description D11 D10 D9 PI11 PI10 PI9 PI3 PI2 PI1 STAC9766/9767 PC AUDIO D8 PVI8 D0 PVI0 D8 PI8 D0 PI0 V 7.4 12/06 ...
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... Tip or Ring selection Bit.This bit sets which jack conductor the sense value is measured from. Software will program the corresponding the Ring/Tip selector bit T/R together with the I/O number in bits FC[3:0 Tip (Left Ring (Right) 71 Description D11 D10 FC2 FC1 FC0 Description STAC9766/9767 PC AUDIO D8 D0 T/R V 7.4 12/06 ...
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... No inversion reported INV 1h - Inverted This bit is read/write and is not reset on RESET#. BIOS should invert for each inverting gain stage. 72 Sense Capability Jack Sense Jack Sense Mic Sense Mic Sense D11 D10 D9 G0 INV DL4 RESERVED Description STAC9766/9767 PC AUDIO D8 DL3 D0 FIP V 7.4 12/06 ...
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... ST[2:0](register 6Ah, Page 01h) are supported and R/W capable. This bit is Read Only. Table 24. Reg 68h Default Values 05h Mic1 06h Mic2 For RESET#: Reg 68h default value is 0000h AUDIO Description Reg 68h Default Value 0010h 0010h 0010h 0010h 0000h STAC9766/9767 V 7.4 12/06 ...
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... RESERVED Bits not used, should read back 0 ) Page 01h D13 D12 ST0 SR5 SR4 74 0 dBV +1.5 dBV +24 dBV -1.5 dBV -24 dBV Bit R/W Overview D11 D10 SPOR DO1 Description D11 D10 SR3 SR2 SR1 STAC9766/9767 PC AUDIO D8 D0 RSVD SR1 V 7.4 12/06 ...
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... Speakers (8 ohms) Speakers (4 ohms) Powered Speakers Stereo Headphone RESERVED RESERVED Headset (mono speaker left channel and mic.) Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with OR[1:0] provide information regarding the type of device sensed. Reserved Unknown (use fingerprint AUDIO Description STAC9766/9767 V 7.4 12/06 ...
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... Major Revision ID. These bits are read only and will be updated based on major MAJORREV device changes. D13 D12 D11 AC97MIX ADCSLT1 ADCSLT0 RSVD MIC GAIN VAL SPLYOVR EN 76 D11 D10 Description D10 D9 RESERVED D2 D1 SPLYOVR VAL STAC9766/9767 PC AUDIO 7.4 12/06 ...
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... Supply Override Value provides the analog voltage operation values. SPLYOVR_VA force 3.3V operation 1 = force 5V operation D13 D12 RESERVED Description = D11 D10 RESERVED STAC9766/9767 PC AUDIO 7.4 12/06 ...
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... RESERVED Reserved 0 = Anti Pop Enabled 1 = Anti Pop Disabled The STAC9766/9767 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the CODEC is powered on and off. This function is accomplished by delaying the charge/discharge of the VREF capacitor (Pin 27). C ...
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... Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a IDT, Inc. assigned code identifying the STAC9766/9767. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) bytes of the Microsoft ID code. The ID2 register (index 7Eh) con- tains the value 7666h, which is the third (76h) byte of the Microsoft ID code, and 66h which is the STAC9766/9767 ID code ...
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... TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING D13 D12 D13 D12 D11 D10 D11 D10 STAC9766/9767 PC AUDIO 7.4 12/06 ...
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... Powerdown Register are performed to power down STAC9766/9767 a section at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values ...
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... Figure 23 illustrates a state when all the mixers work with the static volume settings that are con- tained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9766/9767 to the speakers, with most of the system in low power mode. The procedure for this follows the previous example except that the analog mixer is never shut down. IDT™ ...
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... Secondary CODEC Operation When the STAC9766/9767 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything on the AC-Link will be synchronous Secondary device it can be defined as CODEC ID 01, 10 the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s). IDT™ ...
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... Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0 Secondary CODEC, the STAC9766/9767 will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit CODEC ID value (Slot 0, bits 1 and 0) that matches its configuration ...
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... TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 11.TESTABILITY The STAC9766/9767 has two test modes. One is for ATE in-circuit test and the other is restricted for IDT’s internal use. STAC9766/9767 enters the ATE in-circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 12.ORDERING INFORMATION 12.1. STAC9766/9767 Family Options and Part Order Numbers Part Order Number STAC9766XXTAEyyX STAC9767XXTAEyyX NOTE: When ordering these parts the “yy” will be replaced with the CODEC revision. Add an “R” to the end of any of these part numbers for delivery on Tape and Reel ...
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... CD input, then this pin can be No-Connect. IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Figure 24. Pin Description Drawing 48-Pin TQFP external pulldown. To Disable SPDIF, use AUDIO 24 LINE_IN_R 23 LINE_IN_L 22 MIC2 21 MIC1 20 CD_R 19 CD_GND 18 CD_L 17 VIDEO_R 16 VIDEO_L 15 AUX_R 14 AUX_L 13 PHONE STAC9766/9767 V 7.4 12/06 ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 13.1. Digital I/O These signals connect the STAC9766/9767 to its AC'97 controller counterpart, an external crystal, multi-CODEC selection and external audio amplifier. Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET# No Connect No Connect No Connect GPIO0 ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 13.3. Analog I/O These signals connect the STAC9766/9767 to analog sources and sinks, including microphones and speakers. Pin Name PC-BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L ...
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... TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Table 38. Power and Ground Signals Pin # Type 25 I Analog Vdd = 5 3 Analog Vdd = 5 3 Analog Gnd 42 I Analog Gnd 1 I Digital Vdd = 3 Digital Vdd = 3 Digital Gnd 7 I Digital Gnd 90 PC AUDIO Description STAC9766/9767 V 7.4 12/06 ...
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... Figure 25. 48-Pin LQFP Package Outline and Package Dimensions pin LQFP Pin 1 IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING LQFP Dimensions in mm Key Min Nom A 1.40 1.50 A1 0.05 0.10 A2 1.35 1.40 D 8.80 9.00 D1 6.90 7.00 E 8.80 9.00 E1 6.90 7.00 L 0.45 0.60 e 0. 0.17 0.22 STAC9766/9767 PC AUDIO Max 1.60 0.15 1.45 9.20 7.10 9.20 7.10 0.75 0.20 0.27 V 7.4 12/06 ...
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... C (Ts ) max 60 - 180 seconds Time ( min max o Temperature (T ) 217 C L Time ( 150 seconds L See “Package Classification Reflow Temperatures” on page 93 seconds Ramp-Down rate second max 8 minutes max Figure 26. Solder Reflow Profile 92 PC AUDIO Pb Free Assembly STAC9766/9767 V 7.4 12/06 ...
Page 93
... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING 15.2. Pb Free Process - Package Classification Reflow Temperatures Package Type IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING LQFP 48-pin 93 MSL Reflow Temperature 3 260 STAC9766/9767 PC AUDIO 7.4 12/06 ...
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... SR4 SR3 SR2 CC3 CC2 CC1 CC0 PRE COPY RSVD RV7 RV6 RV5 RV4 RV3 RV2 PVI6 PVI5 PVI4 PVI3 PVI2 STAC9766/9767 PC AUDIO D1 D0 Default ID1 ID0 6A90h MR1 MR0 8000h HPR1 HPR0 8000h MM1 MM0 8000h PV0 RSRVD 0000h GN1 ...
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... FIX RSVD GAIN slot1 slot0 DISBLE VALUE INT APOP RSVD RSVD INTDIS STEREO_MIC RSVD STAC9766/9767 PC AUDIO D1 D0 Default PI1 PI0 FFFFh FC0 T/R 0000h FIP xxxxh DO1 RSVD 0000h SR1 SR0 00xxh SPLY SPLY OVR ...
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... The name of the pin in the AC’97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.” AUDIO STAC9766/9767 V 7.4 12/06 ...
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... STAC9766/9767 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING Innovate with IDT audio for high fidelity. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U ...