S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 84

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N) are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
82
Register. The Configuration Register must be set to the Synchronous Read Mode.
Addresses
AVD#
CLK
WE#
Data
OE#
CE#
V
CC
t
AVSC
t
AS
555h
t
VCS
Figure 14.15 Program Operation Timing Using CLK in Relationship to AVD#
t
CAS
t
CSW
t
Program Command Sequence (last two cycles)
AVCH
t
WP
t
AVDP
A0h
t
AH
t
WC
t
A d v a n c e
WPH
S71WS-Nx0 Based MCPs
PA
t
t
DH
DS
PD
I n f o r m a t i o n
t
CH
VA
t
WHWH1
Progress
Read Status Data
In
S71WS-N_01_A4 September 15, 2005
VA
Complete