S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 135
S71WS256NC0BAWE32
Manufacturer Part Number
S71WS256NC0BAWE32
Description
Stacked Multi-Chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS256NC0BAWE32.pdf
(188 pages)
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September 15, 2005 S71WS-N_01_A4
Latency = 5, Burst Length = 4, WP = Low enable (WE# = V
Last data sustaining
Notes:
1.
2.
3.
LB#, UB#
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
Symbol
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
t
t
t
t
OEL
OLZ
BEL
BLZ
t
AS(B)
A d v a n c e
Valid
WL
WH
0
WZ
or t
): Data available (driven by Latency-1 clock)
High-Z
t
T
t
Min
CSS(B)
ADVS
): Data don’t care (driven by CS# high going edge).
BC
1
1
5
5
t
AWL
ADVH
1
) should not be over 2.5µs.
t
t
Figure 32.5 Timing Waveform of Burst Read Cycle (3)
WL
AH(B)
): Data not available (driven by CS# low going edge or ADV# low going edge)
Don’t C are
Speed
Latency 5
2
Table 32.4 Burst Read AC Characteristics
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
t
t
OLZ
BLZ
3
Max
—
—
—
—
t
t
BEL
OEL
4
t
WH
t
BC
Undefined
Units
clock
5
t
CD
ns
DQ0
6
Symbol
DQ1
t
t
t
t
7
t
WH
WL
CD
OH
OH
DQ2
8
IH
, MRS# = V
DQ3
9
Min
—
—
—
3
10
Speed
11
IH
).
12
Max
10
10
12
—
13
14
Units
ns
133
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