S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 165

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

September 15, 2005 S71WS-N_01_A4
47.3.2
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
Notes:
1.
2.
3.
4.
5.
Note:
UB#, LB#
Address
CS#
WE#
Data in
Data out
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
t
t
t
going high.
In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
CW
AS
WR
Symbol
t
t
t
t
t
t
is measured from the address valid to the beginning of write.
WC
CW
AW
BW
WP
is measured from the CS# going low to the end of write.
is measured from the end of write to the address change. t
WP(min)
A d v a n c e
= 70ns for continuous write operation over 50 times.
55 (note 1)
Table 47.3 Asynchronous Write AC Characteristics
Min
70
60
60
60
Figure 47.4 Timing Waveform Of Write Cycle
Speed
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
High- Z
High-Z
WP
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
t
AS
Max
—
—
—
—
—
Units
ns
t
AW
t
WC
t
CW
t
t
BW
WP
WR
is applied in case a write ends with CS# or WE#
Symbol
t
t
t
t
WR
DW
DH
t
AS
DW
Dat a Valid
t
WR
t
Min
DH
30
0
0
0
High-Z
Speed
WP
is measured from the
Max
—
—
—
—
High-Z
Units
ns
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