S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 144

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

142
Latency = 5, Burst Length = 4 (MRS# = V
Notes:
1.
2.
3.
4.
LB#, UB#
Figure 33.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
WE#
Data in
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
BEADV
Table 33.4 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Symbol
t
WLRL
should be met.
WL
WH
t
AS
WZ
or t
): Data available (driven by Latency-1 clock)
0
): Data don’t care (driven by CS# high going edge)
BC
AWL
Min
) should not be over 2.5µs.
1
1
): Data not available (driven by CS# low going edge or ADV# low going edge)
Speed
t
2
WLRL
High- Z
A d v a n c e
3
Max
S71WS-Nx0 Based MCPs
Read Latency 5
Valid
—
t
t
t
AW
CW
WC
t
t
BW
WP
4
5
High- Z
6
Units
clock
IH
7
Dat a Valid
t
DW
).
I n f o r m a t i o n
t
ADHP
8
t
WR
t
t
ADVS
DH
t
9
AS(B)
Valid
Symbol
10
t
ADHP
t
t
WL
AH(B)
t
11
CSS(B)
t
ADVH
T
Latency 5
12 13
Don’t Ca re
Min
5
14 15 16 17 18
t
t
t
WH
OEL
BEL
t
BC
Speed
S71WS-N_01_A4 September 15, 2005
t
CD
DQ0
Max
—
DQ1
t
OH
DQ2
DQ3
19
Units
t
WZ
ns
t
HZ
20