S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 76

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

74
14.8.3
Data (n + 3)
Data (n + 1)
Data (n + 2)
RDY (n + 3)
RDY (n + 1)
RDY (n + 2)
Addresses
Data (n)
RDY (n)
AVD#
CE#
OE#
CLK
Timing Diagrams
Notes:
1.
2.
3.
t
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
AVC
ACS
Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,
additional clock delay cycles are inserted, and are indicated by RDY.
The device is in synchronous mode.
t
ACH
Aa
t
CR
1
t
CES
t
AVD
2
Figure 14.7 CLK Synchronous Burst Mode Read
t
t
OE
IACC
A d v a n c e
3
5 cycles for initial access shown.
S71WS-Nx0 Based MCPs
4
18.5 ns typ. (54 MHz)
t
RACC
5
t
I n f o r m a t i o n
RDYS
Da
Da
Da
Da
6
t
BDH
Da + 1
Da + 1
Da + 1
Da
t
BACC
7
Da + 2
Da + 2
Da + 1
Da
Da + 3
Da + 2
Da + 1
Da
S71WS-N_01_A4 September 15, 2005
Da + n
Da + n
t
Da + n
Da + n
t
CEZ
OEZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z