S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 110

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

22.2 Mode Register Setting Timing
108
Note:
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then
the mode will be set to the default mode. Each field has its own default mode as indicated. A12 is a reserved bit for future
use. A12 must be set as 0. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion.
The 256 word Full page burst mode needs to meet t
The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, implement
at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.
The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the
transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
In this device, the MRS# pin is used for two purposes. One is to get into the mode register setting
and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting,
the system must drive MRS# pin to V
(drive CS#, ADV#, UB#, LB# and WE# to V
subsequent write command (WE# signal input) is not issued within 0.5µs, then the device might
get into the PAR mode. This device supports software access control type mode register setting
timing. This timing consists of 5 cycles of Read operation. Each cycle of Read Operation is normal
asynchronous read operation. Clock and ADV# are don’t care and WAIT# signal is High-Z. CS#
should be toggling between cycles. The address for 1st, 2nd and 3rd cycle should be 3FFFFF(h)
and the address for 4th cycle should be 3FFEFF. The address for 5th cycle should be MRS code
(Register setting values).
UB#, LB#
A4
MRS#
1
1
ADV#
Address
CS#
WE#
The address bits other than those listed in the table above are reserved. For example, Burst Length address
A3
0
1
Partial Array Refresh
PAR Disable (default)
PAR Enable
PAR
Figure 22.1 Pin MRS Timing Waveform (OE# = V
A d v a n c e
S71WS-Nx0 Based MCPs
t
t
MW
AS
A2
0
1
IL
BC
and immediately (within 0.5µs) issue a write command
(Burst Cycle time) parameter as max. 2500 ns.
Register Write Start
Bottom Array (default)
IL
I n f o r m a t i o n
PAR Array
and drive OE# to V
t
t
Top Array
CW
AW
t
WC
PARA
t
t
WP
BW
IH
A1
0
0
1
1
t
during valid address). If the
WU
A0
0
1
0
1
S71WS-N_01_A4 September 15, 2005
Register Write Complete
IH
)
Register Update Complete
PAR Size
Full Array (default)
1/2 Array
1/4 Array
3/4 Array
PARS