S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 170
S71WS256NC0BAWE32
Manufacturer Part Number
S71WS256NC0BAWE32
Description
Stacked Multi-Chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS256NC0BAWE32.pdf
(188 pages)
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47.3.1.3 Multiple Write Cycle (Low ADV# Type)
MRSE = V
Notes:
1.
2.
3.
4.
5.
6.
7.
Notes:
1.
2.
UB#, LB#
Symbol
CS#
Data out
Low ADV# type multiple write cycle.
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
t
t
t
going high.
Clock input does not have any affect on the asynchronous multiple write operation if t
Latency - 1) clock duration.
t
Low ADV# type multiple write, WE# Controlled.
t
CLK
ADV#
Address
WE#
Data in
CW
AS
WR
WP(min)
WP(min)
t
t
t
t
t
WC
CW
AW
BW
WP
is measured from the address valid to the beginning of write.
is measured from the CS# going low to the end of write.
is measured from the end of write to the address change. t
Table 47.8 Asynchronous Write in Synchronous Mode AC Characteristics
= 70ns for continuous write operation over 50 times.
= 70ns for continuous write operation over 50 times.
Figure 47.9 Timing Waveform Of Multiple Write Cycle (Low ADV# Type)
IH
, OE# = V
55 (note 2)
t
AS
0
Min
70
60
60
60
Speed
IH
1
, WAIT# = High-Z, WE# Controlled\
t
t
t
BW
A d v a n c e
High-Z
AW
CW
2
S71WS-Nx0 Based MCPs
t
WC
WP
t
Max
WP
—
—
—
—
—
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
3
t
DW
Data Valid
Units
4
ns
5
t
I n f o r m a t i o n
WR
t
t
DH
WHP
Symbol
6
t
t
t
t
t
WHP
t
AS
WR
DW
DH
AS
WR
7
is applied in case a write ends with CS# or WE#
Min
5ns
30
0
0
0
8
t
t
t
BW
AW
CW
t
t
WC
WP
9
t
Latency-1 clock
Speed
10
DW
WHP
Dat a Valid
High-Z
S71WS-N_01_A4 September 15, 2005
is shorter than the (Read
Max
—
—
—
—
11
WP
t
WR
is measured from the
t
DH
12
13
Units
ns
—
14
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