S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 183

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

September 15, 2005 S71WS-N_01_A4
Latency = 5, Burst Length = 4 (MRS# = V
Notes:
1.
2.
3.
4.
LB#, UB#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
Symbol
WAIT#
CLK
ADV#
Address
CS#
WE#
OE#
Data in
Data out
t
Table 49.2 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
BEADV
BEADV
Figure 49.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type)
should be met.
A d v a n c e
t
ADVS
t
AS(B)
WL
WH
Valid
WZ
or t
): Data available (driven by Latency-1 clock)
High-Z
1
Min
): Data don’t care (driven by CS# high going edge)
BC
t
7
AWL
T
WL
High-Z
t
) should not be over 2.5µs.
CSS(B)
t
2
ADVH
): Data not available (driven by CS# low going edge or ADV# low going edge)
t
AH(B)
Latency 5
Don’t Ca re
Speed
3
I n f o r m a t i o n
4
S71WS-Nx0 Based MCPs
t
5
Max
t
t
WH
BEL
OEL
—
t
BC
6
t
CD
DQ0
7
Units
IH
DQ1 DQ2
8
ns
t
OH
).
9
10 11
DQ3
Symbol
t
t
t
BEADV
WZ
WLRL
t
HZ
12 13
t
AS
14 15 16 17
Min
1
t
WLRL
Valid Addr e ss
t
AW
High-Z
Read Late ncy 5
Speed
t
t
CW
BW
t
WP
High-Z
18
Max
—
19 20
Dat a Valid
t
DW
t
WR
t
DH
Units
clock
21
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