S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 194

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

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Summary
194
Impact on Extended WRITE Operations
Modified timings are only required during extended WRITE operations (see
83
(t
minimum WRITE cycle time (t
is available for both a refresh operation and successful completion of the WRITE
operation.
CellularRAM products are designed to ensure that any possible bus timings do not
cause corruption of array data due to lack of refresh. The on-chip refresh circuitry
will only affect the required timings for WRITE operations (READs are unaffected)
performed in a system with a slow memory interface. The impact for WRITE op-
erations is that some of the timing parameters (t
modified timings are likely to have little or no impact when interfacing a Cellular-
RAM device with a low-speed memory bus.
WP
below). An extended WRITE operation requires that both the write pulse width
) and the data valid period (t
ADDRESS
LB#/UB#
DATA-IN
WE#
CE#
Figure 82. Extended Timing for t
Figure 83. Extended WRITE Operation
CE#
A d v a n c e
WC[MIN]
CellularRAM-2A
DW
t CEM or t TM > 4µs
) will need to be lengthened to at least the
). These increased timings ensure that time
t
CEM
<
10µs
I n f o r m a t i o n
t WP > t WC (MIN)
t DW > t WC (MIN)
WP
, t
CEM
DW
) are lengthened. The
(2)
cellRAM_02_A0 December 15, 2004
Figure